LM12434 datasheet(32/80 Pages) NSC

32 / 80 page

60 Operational Information (Continued)

INSTRUCTION RAM

(ReadWrite) (Continued)

Limits

D15

D14

D13

D12

D11

D10

Don’t Care

Sign

Limit

D7 – D0

Limit 8-bit limit value

Sign Sign of limit value 0 e Positive 1 e Negative

High LimitLow limit 0 e Inputs lower than limit generate interrupt 1 e Inputs higher than limit generate

interrupt

D15 – D10 Don’t Care

INTERRUPT ENABLE REGISTER

(ReadWrite)

D15

D14

D13

D12

D11

D10

Number of Conversion

Instruction Number

INT7

INT5

INT4

INT3

INT2

INT1

INT0

Results in FIFO to

to Generate

Generate Interrupt (INT2)

Interrupt (INT1)

Bits

0 to 7 enable interrupt generation for the following conditions when the bit is set to 1

INT0 Generates an interrupt when a limit is passed in watchdog mode

INT1 Generates an interrupt when the sequencer has loaded the instruction number contained in bits D10 D9 and

D8 of the Interrupt Enable register

INT2 Generates an interrupt when the number of conversion results in the FIFO is equal to the programmed value

(D15 – D11)

INT3 Generates an interrupt when an auto-zero cycle is completed

INT4 Generates an interrupt when a full calibration cycle is completed

INT5 Generates an interrupt when a pause condition is encountered

This bit is a don’t care condition No interrupt is associated with this bit

INT7 Generates an interrupt when the chip is returned from standby and is ready for operation

D10 – D8

Programmable instruction number used to generate an interrupt when that instruction has been reached

D15 – D11 Programmable number of conversion results in the FIFO to generate an interrupt

TIMER REGISTER

(ReadWrite)

D15

D14

D13

D12

D11

D10

N e Timer Preset Value

The Timer delays the execution of an instruction if the Timer bit is set in that instruction

The time delay is

Delay e (32 c N) a 2 Clock Cycles

FIGURE 9 Bit Assignments for LM12434 and LM12 L 438 Internal Registers

(Continued)

LM12434 Datasheet(PDF) 32 Page - National Semiconductor (TI)

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