AV2188

June 2, 2000

5-20

DVSS

9

GND

Digital ground

XCK

10

I

External Master Clock Input.

SCL

11

I

I2C clock input.

SDA

12

I/O

I2C DATA bus. Open drain ouput. Externally this pin should tie to a 680 ohm pull

up resistor.

TEST

11

O

Test fs reference pin. For test vector verification. For normal operation this pin

must be tied to ‘0’.

RST

12

I

Active low power down reset. When low, the chip is reset and all programmable

registers are reset to default values. Must activate this pin if the P/S or

ADDR[1:0] change state.

Analog

VOL3

28

O

Analog left channel output 3

VOR3

27

O

Analog right channel output 3.

VOL2

26

O

Analog left channel output 2.

VOR2

25

O

Analog right channel output 2.

VOL1

24

O

Analog left channel output 1.

VOR1

23

O

Analog right channel output 1.

AVSS

22

GND

Analog circuits ground

VCM2

21

Common voltage output pin for the DAC.

AVDD

20

+5V

Analog circuits power supply

VCM1

19

Common voltage output pin for the ADC.

AVSS

18

GND

Analog circuits ground

AINR

17

I

ADC right cahnnel input. 1 volt rms input.

AINL

16

I

ADC left channel input. 1 volt rms input.

N/C

15

No connection, should be tied to AVSS

PIN DESCRIPTION (Continued)

Pin Name

Pin #

Type

Description