OV5017

4

Version 1.6

October 20, 1997

Confidential Preliminary Product Specification

1. Video Data Bus

Figure 1. Video Data Timing Showing Continuous Pixel Reading

highest is ‘hff’, no reserved code for blanking or sync.

PCLK

is the pixel clock that is either continuously on or present only during valid pixel window. If the con-

As shown in Figure 1, reading of the video data is not different from reading other on-chip registers, it

requires the assertion of OEB and CSB and the correct address. To maintain uninterrupted video data

stream, OV5017 video data will be updated at each pixel clock as long as the OEB, CSB, and correct

address are asserted as shown in Figure 1.

Since the video data is continuous during the active window, to prevent new data overruns the previous

one, the host has to make sure at least one video data is read in every pixel clock period. The status reg-

ister bit RDY and OV allows host to perform polling and error detection.

1.1 Register Control

The register read/write is the same as normal memory access, using pins DATA[7:0], A[3:0], WEB, OEB,

and CSB. As shown in Figure 2 and Figure 3, the read cycle can be chip select controlled or address

controlled. The write cycle also can be chip select controlled or write enable controlled. The memory

cycle is fully asynchronous to the frame or pixel timing. Write cycle affects only the registers which are

writable, it does not affect read only registers such as video port status register. Since writing to certain

PCLK

OEB

CSB

DATA[7:0]

VD

VD

VD

VD

PIXEL DATA

HREF

PROGRAMMED HORIZONTAL WINDOW WIDTH

VD

VIDEO PORT ADDRESS

A[3:0]