OV5017

6

Version 1.6

October 20, 1997

Confidential Preliminary Product Specification

2. Registers

Note: Unimplemented bits in all the R/W registers return “0” in the read cycle, no effect in the write cycle.

2.1 Detailed Register Descriptions

The following table describes the function of each bit within a register:

Table 2. Register Sets

A[3:0]

Register

Name

R/W

Bit Name

Function

Default

Value

10xx

VPORT

R

VD[7:0]

Video data

xxxxxxxx

0000

STATUS

R

TO2,TO1, , ,OV,

VSYNC, HREF, RDY

Status register

00xxxxxx

0001

FCTL

W

SFR, FSET, , ,

SKIP, FBLC, STOP,

SRST

Single frame flow control

system control

00xx0000

0010

EXCTL

R/W

AUTO, EX[6:0]

Auto or manual exposure

value

11111111

0011

GCTL

R/W

GN[2:0]

Gain value

xxxxx000

0100

FRCTL

R/W

FDIV[5:0]

Frame rate divider

xx000000

0101

MCTL

R/W

GAMMA, MIR, DN,

BKL, FZEX, PCKS,

PCKI, BPSHP

Miscellaneous controls

00000000

0110

HWCTL

R/W

HWS[3:0], HWE[3:0]

Window control

00000000

0111

VWCTL

R/W

VWS[3:0], VWE[3:0]

Window control

00000000

1110

TST

W

TST[7:0]

Reserved for test

xxxxxxxx

1111

TOPT

W

TOPT[7:0]

Reserved for test

xxxxxxxx

Table 3. Bit descriptions

Register

Name

Bit name

Range

Function

VPORT

VD

VD[7:0]

This register selects the video data port. The video data is not latched

in this VPORT, as long as VPORT remains selected. The video data

is updated as new pixel signals are converted.

STATUS

TO2

STA7

Reserved bit.