MP2166

– 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS

MP2166 Rev. 1.0

www.MonolithicPower.com

18

3/14/2017

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PCB Layout Guidelines

(6)

Efficient

PCB

layout

is

critical for

stable

operation.

A

four-layer

layout

is

strongly

recommended

to

achieve

better

thermal

performance. For best results, refer to Figure 6

and follow the guidelines below.

1. Place the high-current paths (PGND, VIN,

and SW) very close to the device with short,

direct, and wide traces.

2. Place input capacitors on both VIN sides

and as close to VIN and PGND as possible.

3. Place the decoupling capacitor as close to

VCC and AGND as possible.

4. Keep the switching node SW short and

away from the feedback network.

5. Place the external feedback resistors next

to FB. Do not place vias on the FB trace.

6. Connect PGND to a large copper area to

achieve better thermal performance.

Top Layer

Inner Layer 1

Inner Layer 2

Bottom Layer

Figure 6: Recommended PCB Layout

NOTE:

6)

The recommended PCB layout is based on Figure7