MP2499M – 36V, 3A MAX, SYNCHRONOUS BUCK CONVERTER

MP2499M Rev 1.0

www.MonolithicPower.com

11

5/1/2018

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© 2018 MPS. All Rights Reserved.

OPERATION

The

MP2499M

is

a

high-frequency,

synchronous, rectified, step-down, switch-mode

converter with built-in power MOSFETs. The

MP2499M offers a very compact solution to

achieve 3A max of continuous output current

with built-in output line drop compensation.

The MP2499M operates in a fixed-frequency,

peak-current-control

mode

to

regulate

the

output voltage. An internal clock initiates a

PWM cycle. The integrated high-side power

MOSFET (HS-FET) turns on and remains on

until its current reaches the value set by the

When the power switch is off, it remains off until

the next clock cycle begins. If the current in the

power MOSFET does not reach the current

value set by COMP within 97% of one PWM

period, the power MOSFET is forced off.

Internal Regulator

The 5V internal regulator powers most of the

A

0.1µF

decoupling

ceramic

capacitor

is

needed at VCC.

Error Amplifier (EA)

The error amplifier (EA) compares the FB

voltage against the internal 0.8V reference

(REF) and outputs a COMP voltage. This

COMP voltage controls the power MOSFET

current. The optimized internal compensation

network minimizes the external component

count and simplifies the control loop design.

Enable/SYNC Control

EN/SYNC is a digital control pin that turns the

regulator on and off. Drive EN/SYNC high to

turn on the regulator; drive EN/SYNC low to

turn off the regulator. EN/SYNC cannot be

floated.

EN/SYNC is clamped internally using a 6.5V

series Zener diode (see Figure 2). Connect the

EN/SYNC input through a pull-up resistor to any

voltage connected to IN. The pull-up resistor

limits the EN/SYNC input current below 150µA.

Connecting EN/SYNC to a voltage source

directly without a pull-up resistor requires

limiting the

voltage amplitude to ≤6V to prevent

damage to the Zener diode.

Figure 2: 6.5V Type Zener Diode

Connect an external clock with a range of

200kHz to 2.4MHz to synchronize the internal

clock rising edge to the external clock rising

edge. The pulse width of the external clock

signal should be less than 3

μs.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MP2499M UVLO comparator monitors the

output voltage of the internal regulator (VCC).

The UVLO rising threshold is about 4.5V, while

its falling threshold is 4.3V.

Internal Soft Start (SS)

Soft start (SS) prevents the converter output

voltage

from

overshooting

during

start-up.

When the chip starts up, the internal circuitry

generates a soft-start voltage that ramps up

from 0V to 1.2V. When SS is lower than REF,

SS overrides REF so the error amplifier uses

SS as the reference. When SS exceeds REF,

the error amplifier uses REF as the reference.

The SS time is set to 1.6ms internally.

Output Line Drop Compensation

The MP2499M is capable of compensating for

an

output

voltage

drop,

such

as

high

impedance caused by a long trace, to maintain

a fairly constant load-side voltage.

The MP2499M uses the sensed load current

Equation (1):

LOAD

SENSE

SINK

IR

I

16.5k





(1)