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MP9943 Datasheet(PDF) 17 Page - Monolithic Power Systems

Part # MP9943
Description  High Efficiency 3A Peak, 36V, Synchronous Step Down Converter With Power Good
PDF  20 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP9943 Datasheet(HTML) 17 Page - Monolithic Power Systems

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MP9943 – 36V, 3A PEAK SYNCHRONOUS STEP-DOWN CONVERTER
MP9943 Rev.1.1
www.MonolithicPower.com
17
7/4/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
VIN is below 5V
VOUT is 5V or 3.3V; and Duty cycle is high:
D=
IN
OUT
V
V
>65%
In these cases, if BST voltage insufficient
happens, the output ripple voltage may become
extremely large at light load condition, add an
external BST diode from the VCC pin or VOUT to
BST pin, as shown in Figure 7.
Figure 7: Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is
1N4148, and the BST capacitor value is 0.1µF to
1μF.
PCB Layout(8)
PCB layout, especially the input capacitor and
VCC capacitor placement, is very important to
achieve stable operation. For the best results,
follow these guidelines:
1) Place the ceramics input capacitor as close to
IN and GND pins as possible, especially the
small package size (0603) input bypass capacitor.
Keep the connection of input capacitor and IN pin
as short and wide as possible.
2) Place the VCC capacitor to VCC pin and GND
pin as close as possible. Make the trace length of
VCC pin-VCC capacitor anode-VCC capacitor
cathode-chip GND pin as short as possible.
3) Use large ground plane directly connect to
GND pin. Add vias near the GND pin if bottom
layer is ground plane.
4) Route SW, BST away from sensitive analog
areas such as FB.
5) Place the T-type feedback resistor close to
chip to ensure the trace which connects to FB pin
as the short as possible.
Notes:
8) The recommended layout is based on the Figure 9 Typical
Application circuit on page 19.
Top Layer
Bottom Layer
Figure 8: Recommended PCB Layout



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