MPQ8632 datasheet(44/47 Pages) MPS

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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A

MPQ8632 Rev.1.26

www.MonolithicPower.com

6/7/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

LAYOUT RECOMMENDATION

1. Place high current paths (GND, IN, and SW)

very close to the device with short, direct and

wide traces.

2. Two-layer IN copper layers are required to

achieve better performance. Place at least

one 0.1uF-1uF 0603 or 0402 decoupling input

capacitor on each side of the IC. The input

capacitors should be placed as close to the

IN and GND pins as possible (maximum 2mm

edge-to-edge distance is allowed). Multiple

vias with 18mil diameter and 8mil hole-size

are required to be placed under the device

and near input capacitors. These vias can

help to reduce the parasitic inductance and

optimize the thermal dissipation.

3. Put a decoupling capacitor as close to the

VCC and AGND pins as possible.

4. Keep the switching node (SW) plane as small

as possible and far away from the feedback

network.

5. Place the external feedback resistors next to

the FB pin. Make sure that there are no vias

on the FB trace. The feedback resistors

should refer to AGND instead of PGND.

6. Keep the BST voltage path (BST, C3, and

SW) as short as possible.

7. Keep FREQ signal away from noise signals,

like SW, BST and VIN plane and vias close to

the MP8632 VIN pins. The VIN pin of

frequency setting resistor (RFREQ) should

connect to a quiet VIN node before input

decoupling capacitor.

8. Strongly recommend a four-layer layout to

improve thermal performance.

FREQ

VCC

PGND

BST

MPQ8632

MPQ8632 H

VIN

RFREQ

AGND

C1A

VOUT

C1B

C1C

C1E

C1D

Figure 55—Schematic for PCB Layout

Guideline

Figure 56—Recommend Input Capacitor

Placement for 16-Pin QFN 3mmx4mm

Package Part, including MPQ8632-4/6/8/10/12

and MPQ8632H-10.

Top Layer

Inner1 Layer

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