LM9801 datasheet(20/34 Pages) NSC

20 / 34 page

Applications Information

10 THEORY OF OPERATION

The LM9801 removes errors from and digitizes a linear CCD

pixel stream while providing all the necessary clock signals

to drive the CCD Offset and gain errors for individual pixels

are removed at the pixel rate Offset errors are removed

through correlated double sampling (CDS) Gain errors

(which may come from any combination of PRNU uneven

illumination cos4 effect RGB filter mismatch etc) are re-

moved through the use of a 8-bit programmable gain ampli-

fier (PGA) in front of the ADC

11 The Analog Signal Path

(See Block Diagram)

The analog output signal from the CCD is connected to the

OS input of the LM9801 through a 001 mF (typical see

Section 42

Clamp Capacitor Selection ) DC blocking capac-

itor During the CCD’s optical black pixel segment at the

beginning of every line this input is clamped to the REF

OUTMID voltage (approximately 245V) This DC restore op-

eration fixes the reference level of the CCD pixel stream at

REF OUTMID

The signal is then buffered and fed to a digitally-pro-

grammed 4-bit VGA (variable gain amplifier) The gain of the

VGA is digitally programmable in 16 steps from 1VV to

3VV The VGA is used to compensate for peak white CCD

outputs less than the 1225V full-scale required by the

LM9801 for maximum dynamic range When used with par-

allel output CCDs the VGA can fine-tune the amplitude of

the red green and blue signals For a detailed explanation

of the VGA see Section 43

The output of the VGA goes into the CDS (Correlated Dou-

ble Sampling) stage consisting of two samplehold amplifi-

ers SH Ref (Reference) and SH Signal The reference

level of the signal is sampled and held by the SH Ref cir-

cuit and the active pixel data is sampled and held by the S

H Signal circuit The output of SH Ref is subtracted from

the SH Signal output and amplified by 2 The full-scale

signal range at this point is approximately 245Vp-p CDS

reduces or eliminates many sources of noise including re-

set noise flicker noise and both high and low frequency

pixel-to-pixel offset variation For more information on the

CDS stage see Section 44

At this point an offset voltage can be injected by the 5-bit (4

bits a sign) Offset DAC This voltage is designed to com-

pensate for any small fixed DC offset introduced by the CDS

SHs and the x2 amplifier The LSB size of the DAC is ap-

proximately 042 ADC LSBs (4 mV) The adjustment range

is g63 ADC LSBs For a detailed explanation of the Offset

DAC see Section 46

The next stage is the PGA This is a programmable gain

amplifier that changes the gain

at the pixel rate to correct

for gain errors due to PRNU uneven illumination (such as

cos4 effect) RGB filter mismatch etc The gain adjustment

range is 0 dB to 9 dB (1VV to 3VV) with 8 bits of resolu-

tion The gain data (correction coefficients) is provided on

the CD0 – CD7 bus The gain may also be fixed at any value

between 0 dB and 9 dB with the PGA Gain Coefficient

configuration register For additional information on the

PGA see Section 47

An approximately 2 LSB (29 mV) offset can be added at the

output of the PGA stage if necessary to ensure that the

offset is greater than zero This eliminates the possibility of

a negative offset clipping the darkest output pixels For

more information on the Offset Add Bit see Section 48

Finally the output of the PGA is digitized by the ADC and

made available on the DD0 – DD7 bus (Section 49)

Three reference voltages are used throughout the signal

path the externally supplied REF IN (1225V) and the inter-

nally generated REF OUTMID (245V) and REF OUTHI

(3675V)

12 The CCD Clocking Signals

To maximize the flexibility of the LM9801 the CCD’s w1

2 RS and TR pulses are internally generated with a wide

range of options making these signals compatible with

most commercial linear CCDs In many cases these output

signals can drive the CCD clock inputs directly with only

series resistors (for slew rate control) between the

LM9801’s outputs and the CCD clock inputs

13 The Digital Interface

There are three main sections to the digital interface of the

LM9801 a serial interface to the Configuration Register

where all device programming is done an 8 bit-wide input

databus for gain correction coefficients with a synchronous

clock output (CCLK) and an 8-bit output databus for the

final pixel output data with a synchronous end of conversion

output signal (EOC) and an output enable input (RD) Please

note that the CS input affects only the serial IO – it has no

effect on the output databus input coefficient bus or any

other section of the LM9801

20 DIGITAL INTERFACE

21 Reading and Writing to the Configuration Register

Communication with the Configuration Register is done

through a standard MICROWIRETM serial interface This in-

terface is also compatible with the Motorola SPITM standard

and is simple enough to easily be implemented in custom

hardware if desired

The serial interface timing is shown in Diagrams 13a – 13b

and Diagrams 15a – 15d Data is sent serially LSB first

(Please note that some microcontrollers output data MSB

first When using these microcontrollers the bits in the con-

figuration register are effectively reversed) Input data is

latched on the rising edge of SCLK and output data chang-

es on the falling edge of SCLK CS must be low to enable

serial IO

If SCLK is only clocked when sending or receiving data from

the LM9801 and held low at all other times then CS can be

tied low permanently as shown in Diagrams 15a – 15d If

SCLK is continuous then CS must be used to determine the

beginning and the end of a serial byte or word (see Dia-

grams 13a – 13b) Note that CS must make its high-to-low

and low-to-high transitions when SCLK is low otherwise the

internal bit counter may receive an erroneous pulse causing

an error in the write or read operation

Data may be transmitted and received in two 8-bit bytes

(typical with microcontroller interfaces) or one 16-bit word

(for custom serial controllers)

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