LM9801CCVF datasheet(27/34 Pages) NSC

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Applications Information (Continued)

60 POWER SUPPLY CONSIDERATIONS

61 General

The LM9801 should be powered by a single a5V source

(unless 3V-compatible digital IO is requiredsee Section

62) The analog supplies (VA) and the digital supplies (VD

and VD(IO)) are brought out individually to allow separate

bypassing for each supply input They should

not be pow-

ered by two or more different supplies

In systems with separate analog and digital a5V supplies

all the supply pins of the LM9801 should be powered by the

analog a5V supply Each supply input should be bypassed

to its respective ground with a 01 mF capacitor located as

close as possible to the supply input pin A single 10 mF

tantalum capacitor should be placed near the VA supply pin

to provide low frequency bypassing

To minimize noise keep the LM9801 and all analog compo-

nents as far as possible from noise generators such as

switching power supplies and high frequency digital busses

If possible isolate all the analog components and signals

(OS reference inputs and outputs VA AGND) on an analog

ground plane separate from the digital ground plane The

two ground planes should be tied together at a single point

preferably the point where the power supply enters the PCB

62 3V Compatible Digital IO

If 3V digital IO operation is desired the VD(IO) pin may be

In this case all the digital IO pins (CD0 – CD7 CCLK

MCLK DD0 – DD7 EOC RD SYNC CS SCLK SDO and

SDI) will be 3V compatible The CCD clock signals (w1 w2

RS and TR) remain 5V outputs powered by VD In this case

the VD(IO) input should be bypassed to DGND(IO) with a

parallel combination of a 01 mF capacitor and a 10 mF tan-

talum capacitor

63 Power Down Mode

Setting the Power Down bit to a ‘‘1’’ puts the device in a low

power standby mode The CCD outputs (w1 w2 RS and

TR) are pulled low and the analog sections are turned off to

conserve power The digital logic will continue to operate if

MCLK continues and SYNC is held high so for minimum

power dissipation MCLK should be stopped when the

LM9801 enters the Power Down mode Recovery from Pow-

er Down typically takes 50 ms (the time required for the

reference voltages to settle to 05 LSB accuracy)

70 COLOR

There are two primary ways to use the LM9801 in a color

system with a triple output (RGB) CCD The first is to use

one LM9801 with an external multiplexer This is the sim-

plest solution The second technique is to use one LM9801

per RGB color

71 Parallel Output CCD One LM9801

Figure 12 is an example of how to use a single LM9801 with

a triple-output RGB CCD In this case an entire line of red is

digitized followed by an entire line of green then blue This

solution provides a 25 Mpixelssec (for an effective 830k

RGB pixelssec after de-interleaving) pixel rate using a high

performance triple output color CCD

The Mux 1 multiplexer located between the CCD’s OS out-

puts and the LM9801’s OS input selects the color to be

digitized according to the states of the A and B inputs (de-

scribed below) The multiplexer’s speed requirements are

minimal because the mux switches at the line rate not the

pixel rate Also since the output of the mux goes into a high

impedance low-capacitance input the ON resistance of the

mux is not critical The 74HC4052 is a good choice for this

application

TLH12814 – 39

FIGURE 12 Parallel Output CCD Application Circuit

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