AD6636PCB datasheet(40/72 Pages) AD

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AD6636

Rev. 0 | Page 40 of 72

2×

POWER OF 2

P POLE

R DESIRED

CLIP

BITS

PROGRAMMABLE

BIT WIDTH

ERROR

K1 GAIN

USED ONLY FOR

DESIRED CLIPPING

LEVEL MODE

GAIN MULTIPLIER

K2 GAIN

E ERROR

THRESHOLD

K× z–1

1 – (1 + P) × z–1 + P × z–2

SQUARE ROOT

AVERAGE 1 – 16384 SAMPLES

DECIMATE 1 – 4096 SAMPLES

log2(x)

MEAN SQUARE (I2 + Q2)

CLIP

Figure 39: Block Diagram of the AGC

Desired Signal Level Mode

In this mode of operation, the AGC strives to maintain the

output signal at a programmable set level. The desired signal

level mode is selected by writing Logic 0 into the AGC clipping

error enable bit of the AGC control register. The loop finds the

square (or power) of the incoming complex data signal by

squaring I and Q and adding them.

The AGC loop has an average and decimate block. This average

and decimate operation takes place on power samples and

before the square root operation. This block can be pro-

grammed to average from 1 to 16,384 power samples, and the

decimate section can be programmed to update the AGC once

every 1 to 4,096 samples. The limitation on the averaging

operation is that the number of averaged power samples should

be a multiple of the decimation value (1×, 2×, 3×, or 4×).

The averaging and decimation effectively means that the AGC

can operate over averaged power of 1 to 16,384 output samples.

Updating the AGC once every 1 to 4,096 samples and operating

on average power facilitates the implementation of the loop

filter with slow time constants, where the AGC error converges

slowly and makes infrequent gain adjustments. It is also useful

when the user wants to keep the gain scaling constant over a

frame of data or a stream of symbols.

Due to the limitation that the number of average samples must

be a multiple of the decimation value, only the multiple

numbers 1, 2, 3, or 4 are programmed. This is set using the AGC

average samples word in the AGC average sample register.

These averaged samples are then decimated with decimation

ratios programmable from 1 to 4,096. This decimation ratio is

defined in the 12-bit AGC update decimation register.

The average and decimate operations are tied together and

implemented using a first-order CIC filter and FIFO registers.

Gain and bit growth are associated with CIC filters and depend

on the decimation ratio. To compensate for the gain associated

with these operations, attenuation scaling is provided before the

CIC filter.

This scaling operation accounts for the division associated with

the averaging operation as well as the traditional bit growth in

CIC filters. Because this scaling is implemented as a bit-shift

operation, only coarse scaling is possible. Fine scaling is

implemented as an offset in the request level, as explained later

in this section. The attenuation scaling SCIC is programmable

from 0 to 14 using a 4-bit CIC scale word in the AGC average

samples register and is given by

(

)

[

]

avg

CIC

ceil

log

where:

MCIC is the decimation ratio (1 to 4,096).

NAVG is the number of averaged samples programmed as a

multiple of the decimation ratio (1, 2, 3, or 4).

For example, if a decimation ratio Mcic is 1,000 and Navg is 3

(decimation of 1,000 and averaging of 3,000 samples), then the

actual gain due to averaging and decimation is 3,000 or 69.54

dB (log2 (3000)). Because attenuation is implemented as a bit-

shift operation, only multiples of 6.02 dB attenuations are

possible. SCIC in this case is 12, corresponding to 72.24 dB. This

way, SCIC scaling always attenuates more than is sufficient to

compensate for the gain in the average and decimate sections

and, therefore, prevents overflows in the AGC loop. But it is also

evident that the SCIC scaling induces a gain error (the difference

between gain due to CIC and attenuation provided by scaling)

of up to 6.02 dB. This error should be compensated for in the

request signal level, as explained later in this section.

A logarithm to the Base 2 is applied to the output from the

average and decimate section. These decimated power samples

are converted to rms signal samples by applying a square root

operation. This square root is implemented using a simple shift

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