AD6636PCB datasheet(61/72 Pages) AD

61 / 72 page

AD6636

Rev. 0 | Page 61 of 72

<2>: Port CD Amplitude Correction Enable Bit. When this bit is

set, the amplitude correction function of the I/Q correction

logic for the AB port is enabled. When this bit is cleared, the

amplitude correction value is given by the value of the AB

amplitude correction register. If the Port A complex data active

bit of the ADC input control register is cleared (real input

mode), this bit is a don’t care.

<1>: Port CD Phase Correction Enable Bit. When this bit is set,

the phase correction function of the I/Q correction logic for the

AB port is enabled. When this bit is cleared, the phase

correction value is given by the value of the AB phase

correction register. If the Port A complex data active bit of the

ADC input control register is cleared (real input mode), this bit

is a don’t care.

<0>: Port CD DC Correction Enable Bit. When the dc

correction enable bit is set, the dc offset correction function of

the I/Q correction block for the AB port is enabled. When

cleared, the dc offset correction value is given by the value of

the AB offset correction registers. If the Port A complex data

active bit of the ADC input control register is cleared (real input

mode), this bit is a don’t care.

Port AB, DC Offset Correction I <15:0>

This register holds the in-phase signal dc offset correction value

for complex data stream when dc correction is enabled. This

value should be set manually when automatic correction is

disabled. This 16-bit value is subtracted from the 16-bit ADC

Port A data (in-phase signal). This data is a don’t care in real

input mode.

Port AB, DC Offset Correction Q <15:0>

This register holds the quadrature phase signal dc offset

correction value for complex data stream when dc correction

enabled. This value should be set manually when automatic

correction is disabled. This 16-bit value is subtracted from the

16-bit ADC Port B data (quadrature phase signal). This data is a

don’t care in real input mode.

Port CD, DC Offset Correction I <15:0>

This register holds the in-phase signal dc offset correction value

for complex data stream when dc correction is enabled. This

value should be set manually when automatic correction is

disabled. This 16-bit value is subtracted from the 16-bit ADC

Port C data (in-phase signal). This data is a don’t care in real

input mode.

Port CD, DC Offset Correction Q <15:0>

This register holds the quadrature phase signal dc offset

correction value for complex data stream when dc correction is

enabled. This value should be set manually when automatic

correction is disabled. This 16-bit value is subtracted from the

16-bit ADC Port D data (quadrature phase signal). This data is a

don’t care in real input mode.

Port AB, Phase Offset Correction <15:0>

This register holds the phase offset correction value for complex

data stream when the AB port phase correction is enabled. This

value is set manually when automatic correction is disabled.

This value is calculated as tan(phase_mismatch), where

phase_mismatch is the mismatch in phase between I (in-phase

signal) and Q (quadrature phase signal). This 14-bit value is

multiplied with 16-bit Q (quadrature phase signal, Input Port B)

and added to 16-bit I (in-phase signal, Input Port A). This data

is a don’t care in real input mode.

Port AB, Amplitude Offset Correction <15:0>

This register holds the amplitude offset correction value for

complex data stream when the AB port amplitude correction is

enabled. This value is set manually when automatic correction

is disabled. This value is calculated as (Mag(Q) − Mag(I)),

where I is the in-phase signal and Q is the quadrature phase

signal. This 14-bit value is multiplied with 16-bit Q (quadrature

phase signal, Input Port B) and added to 16-bit Q (quadrature

phase signal, Input Port B). This data is a don’t care in real input

mode.

Port CD, Phase Offset Correction <15:0>

This register holds the phase offset correction value for the

complex data stream when CD port phase correction is enabled.

This value should be set manually when automatic correction is

disabled. This value should be calculated as tangent

(phase_mismatch), where phase_mismatch is the mismatch in

phase between I (in-phase signal) and Q (quadrature phase

signal). This 14-bit value is multiplied with 16-bit Q

(quadrature phase signal, Input Port D) and added to 16-bit I

(in-phase signal, Input Port C). This data is a don’t care in real

input mode.

Port CD, Amplitude Offset Correction <15:0>

This register holds the amplitude offset correction value for

complex data stream when CD port amplitude correction is

enabled. This value is set manually when automatic correction

is disabled. This value is calculated as (Mag(Q) − Mag(I)),

where I is the in-phase signal and Q is the quadrature phase

signal. This 14-bit value are multiplied with 16-bit Q

(quadrature phase signal, Input Port D) and added to 16-bit Q

(quadrature phase signal, Input Port D). This data is a don’t care

in real input mode.

Port A Gain Control <7:0>

<7>: This bit is open.

<6:1>: This 6-bit word specifies the relinearization pipe delay to

be used in the ADC input gain control block. The decimal

representation of these bits is the number of input clock cycle

pipeline delays between the external EXP data output and the

internal application of relinearization based on EXP.

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