AD6636PCB datasheet(58/72 Pages) AD

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AD6636

Rev. 0 | Page 58 of 72

LVDS Control Register <10:0>

<10>: CMOS Mode Bit. When this bit is set, the ADC ports

operate in CMOS mode. When this bit is cleared, the ADC ports

operate in LVDS mode. The default is Logic 1 or CMOS mode.

In LVDS mode, two CMOS ADC port pins are used to form one

differential pair of LVDS ADC ports.

<9>: Reserved. This bit should always be written Logic 1.

<8>: Autocalibrate Enable Bit. When this bit is set, the auto-

calibration cycle is invoked for the LVDS pads. At the end of

calibration, this calibration value is set for the LVDS pads.

When this bit is cleared, the output for the LVDS controller is

taken from manual calibration value (Bits <7:0> of this

<7:4>: These bits are open.

<3:0>: Manual Calibration Value Bits. The value of these bits is

used for manual LVDS calibration. When the autocalibrate bit is

set, these bits are don’t care.

Interrupt Status Register <15:0>

This register is read-only.

<15>: AGC 5 RSSI Update Interrupt Bit. If the AGC 5 update

interrupt enable bit is set, this bit is set by the AD6636 whenever

AGC 5 updates a new RSSI word (the new word should be

different from the previous word). If the AGC 5 update

interrupt enable bit is cleared, then this bit is not set (not

updated). An interrupt is not generated in this case.

Note: For Bits <15:10>, no interrupt is generated, if the new

RSSI word is the same as the previous RSSI word.

<14>: AGC 4 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC 4.

<13>: AGC 3 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC 3.

<12>: AGC 2 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC 2.

<11>: AGC 1 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC 1.

<10>: AGC 0 RSSI Update Interrupt Bit. Similar to Bit <15> for

the AGC 0.

<9>: Channel 5 Data Ready Interrupt Bit. This bit is set to

Logic 1 whenever the channel BIST signature registers are

loaded with data. The conditions required for setting this bit

are: the channel BIST signature registers is programmed for

BIST signature generation and the Channel 5 data ready enable

bit in the interrupt enable register is cleared. If the Channel 5

data ready enable bit in the interrupt enable register is set, the

AD6636 does not set this bit on signature generation and an

interrupt is not generated.

<8>: Channel 4 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 4.

<7>: Channel 3 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 3.

<6>: Channel 2 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 2.

<5>: Channel 1 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 1.

<4>: Channel 0 Data Ready Interrupt Bit. Similar to Bit <9> for

Channel 0.

<3>: ADC Port D Power Monitoring Interrupt Bit. This bit is set

by the AD6636 whenever the ADC Port D power monitor

interrupt enable bit is set and the Port D power monitor timer

runs out (end of the Port D power monitor period). If the ADC

Port D power monitoring interrupt enable bit is cleared, the

AD6636 does not set this bit and does not generate an interrupt.

Note: In real input CMOS mode, all four input ports exist. In

complex input CMOS mode, only ADC Ports A and C function.

In real input LVDS mode, only ADC Ports A and C function.

<2>: ADC Port C Power Monitoring Interrupt Bit. Similar to

Bit <3> for ADC Port C.

<1>: ADC Port B Power Monitoring Interrupt Bit. Similar to

Bit <3> for ADC Port B.

<0>: ADC Port A Power Monitoring Interrupt Bit. Similar to

Bit <3> for ADC Port A.

Interrupt Enable Register <15:0>

<15>: AGC 5 RSSI Update Enable Bit. When this bit is set, the

AGC 5 RSSI update interrupt is enabled, allowing an interrupt

to be generated when the RSSI word is updated. When this bit is

cleared, an interrupt cannot be generated for this event. Also,

see the Interrupt Status Register <15:0> section.

<14>: AGC 4 RSSI Update Enable Bit. Similar to Bit <15> for

the AGC 4.

<13>: AGC 3 RSSI Update Enable Bit. Similar to Bit <15> for

the AGC 3.

<12>: AGC 2 RSSI Update Enable Bit. Similar to Bit <15> for

the AGC 2.

<11>: AGC 1 RSSI Update Enable Bit. Similar to Bit <15> for

the AGC 1.

<10>: AGC 0 RSSI Update Enable Bit. Similar to Bit <15> for

the AGC 0.

AD6636PCB Datasheet(PDF) 58 Page - Analog Devices

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