COP682C datasheet(14/30 Pages) NSC

14 / 30 page

Functional Description (Continued)

TLDD10802 – 8

FIGURE 6 Interrupt Block Diagram

DETECTION OF ILLEGAL CONDITIONS

The device contains a hardware mechanism that allows it to

detect illegal conditions which may occur from coding er-

rors noise and ‘brown out’ voltage drop situations Specifi-

cally it detects cases of executing out of undefined ROM

area and unbalanced stack situations

Reading an undefined ROM location returns 00 (hexadeci-

mal) as its contents The opcode for a software interrupt is

also ‘00’ Thus a program accessing undefined ROM will

cause a software interrupt

Reading an undefined RAM location returns an FF (hexade-

cimal) The subroutine stack grows down for each subrou-

tine call By initializing the stack pointer to the top of RAM

the first unbalanced return instruction will cause the stack

pointer to address undefined RAM As a result the program

will attempt to execute from FFFF (hexadecimal) which is

an undefined ROM location and will trigger a software inter-

rupt

MICROWIREPLUSTM

MICROWIREPLUS is a serial synchronous bidirectional

communications interface The MICROWIREPLUS capabil-

ity enables the device to interface with any of National

Semiconductor’s MICROWIRE peripherals (ie AD con-

verters display drivers EEPROMS etc) and with other mi-

crocontrollers which support the MICROWIREPLUS inter-

face It consists of an 8-bit serial shift register (SIO) with

serial data input (SI) serial data output (SO) and serial shift

clock (SK)

Figure 7 shows the block diagram of the MICRO-

WIREPLUS interface

The shift clock can be selected from either an internal

source or an external source Operating the MICROWIRE

PLUS interface with the internal clock source is called the

Master mode of operation Similarly operating the MICRO-

WIREPLUS interface with an external shift clock is called

the Slave mode of operation

The CNTRL register is used to configure and control the

MICROWIREPLUS mode To use the MICROWIREPLUS

the MSEL bit in the CNTRL register is set to one The SK

clock rate is selected by the two bits SL0 and SL1 in the

CNTRL register Table III details the different clock rates

that may be selected

TABLE III

SL1

SL0

SK Cycle Time

2tC

4tC

8tC

where

tC is the instruction cycle clock

MICROWIREPLUS OPERATION

Setting the BUSY bit in the PSW register causes the MI-

CROWIREPLUS arrangement to start shifting the data It

gets reset when eight data bits have been shifted The user

may reset the BUSY bit by software to allow less than 8 bits

to shift The devoce may enter the MICROWIREPLUS

mode either as a Master or as a Slave

Figure 8 shows how

two COP880C microcontrollers and several peripherals may

be interconnected using the MICROWIREPLUS arrange-

ment

Master MICROWIREPLUS Operation

In the MICROWIREPLUS Master mode of operation the

shift clock (SK) is generated internally The MICROWIRE

PLUS Master always initiates all data exchanges (See

Fig-

ure 8 ) The MSEL bit in the CNTRL register must be set to

enable the SO and SK functions onto the G Port The SO

and SK pins must also be selected as outputs by setting

appropriate bits in the Port G configuration register Table IV

summarizes the bit settings required for Master mode of

operation

SLAVE MICROWIREPLUS OPERATION

In the MICROWIREPLUS Slave mode of operation the SK

clock is generated by an external source Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port The SK pin must be selected as an input

and the SO pin is selected as an output pin by appropriately

setting up the Port G configuration register Table IV sum-

marizes the settings required to enter the Slave mode of

operation

The user must set the BUSY flag immediately upon entering

the Slave mode This will ensure that all data bits sent by

the Master will be shifted properly After eight clock pulses

the BUSY flag will be cleared and the sequence may be

repeated (See

Figure 8 )

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