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LTM2892

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Table 3. Unidirectional SPI Timing Event Description

TIME

CPHA

EVENT DESCRIPTION

0, 1

Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns.

t0-t1

0, 1

Propagation delay chip select, logic to isolated side.

Start of data transmission, data setup.

Start of transmission, data and clock setup. Data transition must be within –13ns to 3ns of clock edge.

t2-t3

Propagation delay of data, logic side to isolated side.

Propagation delay of data and clock, logic side to isolated side.

0, 1

Logic side data sample time, half clock period delay from data setup transition.

t3-t5

0, 1

Clock propagation delay, clock and data transition.

t4-t5

0, 1

Data to clock delay, must be ≤ 13ns.

t5-t6

0, 1

Clock to data delay, must be ≤ 3ns.

t5-t7

0, 1

Data and clock propagation delay.

Last clock and data transition.

Last clock transition.

t8-t9

Clock and data propagation delay.

Clock propagation delay.

t9-t10

Data propagation delay.

t11

0, 1

Asynchronous chip select transition, end of transmission.

t12

0, 1

Chip select transition isolated side.

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