LTM4613 datasheet(19/30 Pages) LINER

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LTM4649

4649fc

For more information www.linear.com/LTM4649

APPLICATIONS INFORMATION

the bottom of the part through the solder joints and

through a portion of the board. The board temperature

is measured a specified distance from the package.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 8; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the µModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal oper-

ating conditions of a μModule regulator. For example, in

normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package—as the standard defines

for

θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4649, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to different

junctions of components or die are not exactly linear with

respect to total package power loss. To reconcile this

complication without sacrificing modeling simplicity—

but also, not ignoring practical realities—an approach

has been taken using FEA software modeling along with

laboratory testing in a controlled-environment chamber

to reasonably define and correlate the thermal resistance

valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware

is used to accurately build the mechanical geometry of

the LTM4649 and the specified PCB with all of the cor-

rect material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

defined JEDEC environment consistent with JESD51-12

to predict power loss heat flow and temperature readings

at different interfaces that enable the calculation of the

JEDEC-defined thermal resistance values; (3) the model

and FEA software is used to evaluate the LTM4649 with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

loss as that which was simulated. The outcome of this

process and due diligence yields the set of derating curves

shown in this data sheet. After these laboratory tests have

been performed and correlated to the LTM4649 model,

then the

θJB and θBA values are summed together to

correlate quite well with the µModule model for

θJA with

Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients

4649 F08

µMODULE DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

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