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LTC3858-2

38582f

OPERATION (Refer to the Functional Diagram)

The switching frequency of the LTC3858-2’s controllers

can be selected using the FREQ pin.

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to SGND, tied to

INTVCC or programmed through an external resistor. Tying

FREQ to SGND selects 350kHz while tying FREQ to INTVCC

selects 535kHz. Placing a resistor between FREQ and SGND

allows the frequency to be programmed between 50kHz

and 900kHz, as shown in Figure 10.

A phase-locked loop (PLL) is available on the LTC3858-2

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

phase detector adjusts the voltage (through an internal

lowpass filter) of the VCO input to align the turn-on of

controller 1’s external top MOSFET to the rising edge of

the synchronizing signal. Thus, the turn-on of controller 2’s

external top MOSFET is 180 degrees out of phase to the

rising edge of the external clock source.

The VCO input voltage is pre-biased to the operating

frequency set by the FREQ pin before the external clock

is applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG1. The ability to

pre-bias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

The typical capture range of the phase-locked loop is from

approximately 55kHz to 1MHz, with a guarantee over all

manufacturing variations to be between 75kHz and 850kHz.

In other words, the LTC3858-2’s PLL is guaranteed to lock

to an external clock source whose frequency is between

75kHz and 850kHz.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.1V (falling).

In forced continuous operation or when clocked by an

external clock source to use the phase-locked loop (see

the Frequency Selection and Phase-Locked Loop section),

the inductor current is allowed to reverse at light loads

or under large transient conditions. The peak inductor

current is determined by the voltage on the ITH pin, just

as in normal operation. In this mode, the efficiency at light

loads is lower than in Burst Mode operation. However,

continuous operation has the advantages of lower output

voltage ripple and less interference to audio circuitry. In

forced continuous mode, the output ripple is independent

of load current.

When the PLLIN/MODE pin is connected for pulse-skipping

mode, the LTC3858-2 operates in PWM pulse-skipping

mode at light loads. In this mode, constant frequency

operation is maintained down to approximately 1% of

designed maximum output current. At very light loads, the

current comparator, ICMP, may remain tripped for several

cycles and force the external top MOSFET to stay off for

the same number of cycles (i.e., skipping pulses). The

inductor current is not allowed to reverse (discontinuous

operation). This mode, like forced continuous operation,

exhibits low output ripple as well as low audio noise and

reduced RF interference when compared to Burst Mode

operation. It provides higher light load efficiency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

The selection of switching frequency is a trade-off between

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

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