LTC3891 datasheet(20/40 Pages) LINER

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LTC3858-2

38582f

APPLICATIONS INFORMATION

CIN and COUT Selection

The selection of CIN is simplified by the 2-phase architec-

ture and its impact on the worst-case RMS current drawn

through the input network (battery/fuse/capacitor). It can be

shown that the worst-case capacitor RMS current occurs

when only one controller is operating. The controller with

the highest (VOUT)(IOUT) product needs to be used in the

formula shown in Equation 1 to determine the maximum

RMS capacitor current requirement. Increasing the out-

put current drawn from the other controller will actually

decrease the input RMS ripple current from its maximum

value. The out-of-phase technique typically reduces the

input capacitor’s RMS ripple current by a factor of 30%

to 70% when compared to a single phase power supply

solution.

In continuous mode, the source current of the top MOSFET

is a square wave of duty cycle (VOUT)/(VIN). To prevent

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

CIN Required IRMS ≈

IMAX

VIN

VOUT

() VIN –VOUT

()

⎡⎣

⎤⎦

1/ 2 (1)

Equation 1 has a maximum at VIN = 2VOUT, where IRMS

= IOUT/2. This simple worst-case condition is commonly

used for design because even significant deviations do not

offer much relief. Note that capacitor manufacturers’ ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operating frequency of the LTC3858-2, ceramic capacitors

can also be used for CIN. Always consult the manufacturer

if there is any question.

The benefit of 2-phase operation can be calculated by

using Equation 1 for the higher power controller and

then calculating the loss that would have resulted if both

controller channels switched on at the same time. The

total RMS power lost is lower when both controllers are

operating due to the reduced overlap of current pulses

required through the input capacitor’s ESR. This is why

the input capacitor’s requirement calculated above for the

worst-case controller is adequate for the dual controller

design. Also, the input protection fuse resistance, battery

resistance, and PC board trace resistance losses are also

reduced due to the reduced peak currents in a 2-phase

system. The overall benefit of a multiphase design will

only be fully realized when the source impedance of the

power supply/battery is included in the efficiency testing.

The drains of the top MOSFETs should be placed within

1cm of each other and share a common CIN (s). Separat-

ing the sources and CIN may produce undesirable voltage

and current resonances at VIN.

A small (0.1μF to 1μF) bypass capacitor between the chip

VIN pin and ground, placed close to the LTC3858-2, is also

suggested. A small (1Ω to 10Ω) resistor placed between

CIN (C1) and the VIN pin provides further isolation between

the two channels.

The selection of COUT is driven by the effective series

resistance (ESR). Typically, once the ESR requirement

is satisfied, the capacitance is adequate for filtering. The

output ripple (ΔVOUT) is approximated by:

ΔVOUT ≈ΔIL ESR +

8• f • COUT

⎛

⎝

⎜

⎞

⎠

⎟

where fO is the operating frequency, COUT is the output

capacitance and ΔIL is the ripple current in the inductor.

The output ripple is highest at maximum input voltage

since ΔIL increases with input voltage.

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