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LT3085 Datasheet(PDF) 5 Page - Linear Technology

Part # LT3085
Description  20V, 500mA, Ultralow Noise, Ultrahigh PSRR Linear Regulator with VIOC Control
PDF  36 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT3085 Datasheet(HTML) 5 Page - Linear Technology

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LT3045-1
5
30451fa
For more information www.linear.com/LT3045-1
ELECTRICAL CHARACTERISTICS
Note 6: GND pin current is tested with VIN = VOUT(NOMINAL) and a current
source load. Therefore, the device is tested while operating in dropout. This
is the worst-case GND pin current. GND pin current decreases at higher
input voltages. Note that GND pin current does not include SET pin or ILIM
pin current but Quiescent current does include them.
Note 7: SET and OUTS pins are clamped using diodes and two 25Ω series
resistors. For less than 5ms transients, this clamp circuitry can carry
more than the rated current. Refer to Applications Information for more
information.
Note 8: Adding a capacitor across the SET pin resistor decreases output
voltage noise. Adding this capacitor bypasses the SET pin resistor’s
thermal noise as well as the reference current’s noise. The output noise
then equals the error amplifier noise. Use of a SET pin bypass capacitor
also increases start-up time.
Note 9: The LT3045-1 is tested and specified under pulsed load conditions
such that TJ ≈ TA. The LT3045-1E is 100% tested at 25°C and performance
is guaranteed from 0°C to 125°C. Specifications over the –40°C to 125°C
operating temperature range are assured by design, characterization, and
correlation with statistical process controls. The LT3045-1I is guaranteed
over the full –40°C to 125°C operating temperature range. High junction
temperatures degrade operating lifetimes. Operating lifetime is derated at
junction temperatures greater than 125°C.
Note 10: Parasitic diodes exist internally between the VIOC, ILIM, PG,
PGFB, SET, OUTS, and OUT pins and the GND pin. Do not drive these pins
more than 0.3V below the GND pin during a fault condition. These pins
must remain at a voltage more positive than GND during normal operation.
Note 11: The current limit programming scale factor is specified while the
internal backup current limit is not active. Note that the internal current
limit has foldback protection for VIN – VOUT differentials greater than 12V.
Note 12: The internal back-up current limit circuitry incorporates foldback
protection that decreases current limit for VIN – VOUT > 12V. Some level of
output current is provided at all VIN – VOUT differential voltages. Consult the
Typical Performance Characteristics graph for current limit vs VIN – VOUT.
Note 13: For output voltages less than 1V, the LT3045-1 requires a 10µA
minimum load current for stability.
Note 14: Maximum OUT-to-OUTS differential is guaranteed by design.
Note 15: The VIOC buffer outputs a voltage equal to VIN – VOUT or
VIN – 1.5V (for VOUT ≤ 1.5V). See Block Diagram and Applications
Information for further information. The VIOC pin’s source current should
be set between 10µA and 200µA.



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