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LTC2358-16

Rev A

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APPLICATIONS INFORMATION

OVERVIEW

The LTC2358-16 is a 16-bit, low noise 8-channel simul-

taneous sampling successive approximation register

(SAR) ADC with buffered differential, wide common

mode range picoamp inputs. The ADC operates from a

5V low voltage supply and flexible high voltage supplies,

nominally ±15V. Using the integrated low-drift reference

and buffer (VREFBUF = 4.096V nominal), each channel of

this SoftSpan ADC can be independently configured on a

conversion-by-conversion basis to accept ±10.24V, 0V to

10.24V, ±5.12V, or 0V to 5.12V signals. The input signal

range may be expanded up to ±12.5V using an external

5V reference. Individual channels may also be disabled to

increase throughput on the remaining channels.

The integrated picoamp-input analog buffers, wide input

common mode range, and 128dB CMRR of the LTC2358-

16 allow the ADC to directly digitize a variety of signals

using minimal board space and power. This input signal

flexibility, combined with ±1LSB INL, no missing codes

at 16 bits, and 94.2dB SNR, makes the LTC2358-16 an

ideal choice for many high voltage applications requiring

wide dynamic range.

The absolute common mode input range (VEE + 4V to

VCC – 4V) is determined by the choice of high voltage

supplies. These supplies may be biased asymmetrically

around ground and include the ability for VEE to be tied

directly to ground.

The LTC2358-16 supports pin-selectable SPI CMOS (1.8V

to 5V) and LVDS serial interfaces, enabling it to com-

municate equally well with legacy microcontrollers and

modern FPGAs. In CMOS mode, applications may employ

between one and eight lanes of serial output data, allowing

the user to optimize bus width and data throughput. The

LTC2358-16 typically dissipates 219mW when converting

eight channels simultaneously at 200ksps per channel.

Optional nap and power down modes may be employed to

furtherreducepowerconsumptionduringinactiveperiods.

CONVERTER OPERATION

The LTC2358-16 operates in two phases. During the ac-

quisition phase, the sampling capacitors in each channel’s

sample-and-hold (S/H) circuit connect to their respective

analog input buffers, which track the differential analog

input voltage (VIN+ – VIN–). A rising edge on the CNV pin

transitions all channels’ S/H circuits from track mode to

hold mode, simultaneously sampling the input signals

on all channels and initiating a conversion. During the

conversion phase, each channel’s sampling capacitors

are connected, one channel at a time, to a 16-bit charge

redistribution capacitor D/A converter (CDAC). The CDAC

is sequenced through a successive approximation algo-

rithm, effectively comparing the sampled input voltage

with binary-weighted fractions of the channel’s SoftSpan

full-scale range (e.g., VFSR/2, VFSR/4 … VFSR/65536) us-

ing a differential comparator. At the end of this process,

the CDAC output approximates the channel’s sampled

analog input. Once all channels have been converted in

this manner, the ADC control logic prepares the 16-bit

digital output codes from each channel for serial transfer.

TRANSFER FUNCTION

TheLTC2358-16digitizeseachchannel’sfull-scalevoltage

range into 216 levels. In conjunction with the ADC master

reference voltage, VREFBUF, a channel’s SoftSpan configu-

ration determines its input voltage range, full-scale range,

LSB size, and the binary format of its conversion result, as

shown in Tables 1a and 1b. For example, employing the

internal reference and buffer (VREFBUF = 4.096V nominal),

SoftSpan 7 configures a channel to accept a ±10.24V bi-

polar analog input voltage range, which corresponds to a

20.48Vfull-scalerangewitha312.5μVLSB.OtherSoftSpan

configurationsandreferencevoltagesmaybeemployedto

convert both larger and smaller bipolar and unipolar input

ranges. Conversion results are output in two’s comple-

ment binary format for all bipolar SoftSpan ranges, and

in straight binary format for all unipolar SoftSpan ranges.

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