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LTC2358-16

Rev A

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draws only a small regulator standby current resulting in a

typical power dissipation of 0.68mW. To exit power down

mode, bring the PD pin low and wait at least 10ms before

initiating a conversion. When employing the internal refer-

ence buffer, allow 200ms for the buffer to power up and

recharge the REFBUF bypass capacitor. Any conversion

initiated before these times will produce invalid results.

Reset Timing

A global reset of the LTC2358-16, equivalent to a power-

on-reset event, may be executed without needing to cycle

the supplies. This feature is useful when recovering from

system-level events that require the state of the entire sys-

tem to be reset to a known synchronized value. To initiate

a global reset, bring PD high twice without an intervening

conversion, as shown in Figure 14. The reset event is trig-

geredonthesecondrisingedgeofPD,andasynchronously

ends based on an internal timer. Reset clears all serial data

outputregistersandrestorestheinternalSoftSpanconfigu-

ration register default state of all channels in SoftSpan 7.

If reset is triggered during a conversion, the conversion

is immediately halted. The normal power down behavior

associatedwithPDgoinghighisnotaffectedbyreset.Once

PD is brought low, wait at least 10ms before initiating a

conversion. When employing the internal reference buffer,

allow 200ms for the buffer to power up and recharge the

REFBUF bypass capacitor. Any conversion initiated before

these times will produce invalid results.

Power Dissipation vs Sampling Frequency

When nap mode is employed, the power dissipation of

the LTC2358-16 decreases as the sampling frequency is

APPLICATIONS INFORMATION

reduced, as shown in Figure 15. This decrease in aver-

age power dissipation occurs because a portion of the

LTC2358-16 circuitry is turned off during nap mode, and

the fraction of the conversion cycle (tCYC) spent napping

increases as the sampling frequency (fSMPL)isdecreased.

IOVDD

IVDD

IVEE

IVCC

WITH NAP MODE

tCNVL = 1µs

SAMPLING FREQUENCY (kHz)

120

160

200

–6

–4

–2

235816 F15

Figure 15. Power Dissipation of the LTC2358-16

Decreases with Decreasing Sampling Frequency

DIGITAL INTERFACE

TheLTC2358-16featuresCMOSandLVDSserialinterfaces,

selectable using the LVDS/CMOS pin. The flexible OVDD

supply allows the LTC2358-16 to communicate with any

CMOS logic operating between 1.8V and 5V, including

2.5V and 3.3V systems, while the LVDS interface supports

low noise digital designs. In CMOS mode, applications

may employ between one and eight lanes of serial data

output, allowing the user to optimize bus width and data

throughput. Together, these I/O interface options enable

the LTC2358-16 to communicate equally well with legacy

microcontrollers and modern FPGAs.

CNV

tCONV

tCNVH

tPDH

tPDL

BUSY

RESET

RESET TIME

SET INTERNALLY

SECOND RISING EDGE OF

PD TRIGGERS RESET

tWAKE

235816 F14

Figure 14. Reset Timing for the LTC2358-16

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