MP2626 datasheet(32/34 Pages) MPS

32 / 34 page

MP2626 – SINGLE CELL LI-ION SWITCHING CHARGER WITH USB OTG

MP2626 Rev. 1.0

www.MonolithicPower.com

2/28/2015

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same as the output voltage ripple from equation

(28).

Both charge mode and boost mode have the

same battery voltage ripple. The capacitor CBATT

can be calculated as:

MAX

BATT

BATT _ MAX

1V / V _

−

×Δ

× ×

(29)

To guarantee the

±0.5% BATT voltage accuracy,

the maximum BATT voltage ripple must not

exceed 0.5% (e.g. 0.2%). The worst case occurs

at the minimum battery voltage of the CC charge

with the maximum input voltage.

For

VINMAX=6V,

VCC_MIN=VTC=3V,

L=4.4

μH,

fSW=600kHz or 1.2MHz, ΔrBATT_MAX=0.1%, CBATT is

8.9

μF (for a 600kHz switching frequency) or

5.6

μF (for a 1.2MHz switching frequency).

A 22

μF ceramic with X7R dielectrics capacitor

will suffice.

PCB LAYOUT GUIDE

PCB layout is very important to meet specified

noise, efficiency and stability requirements. The

following design considerations can improve

circuit performance:

1) Route the power stage adjacent to their

grounds. Aim to minimize the high-side switching

node (SW, inductor) trace lengths in the high-

current paths

Keep the switching node short and away from all

small control signals, especially the feedback

network.

Place the input capacitor as close as possible to

the VIN and PGND pins. The local power input

capacitors, connected from the PMID to GND,

must be placed as close as possible to the IC.

Place the output inductor close to the IC and

connect the output capacitor between the

inductor and PGND of the IC.

2) For high-current applications, the power pads

for IN, SW, BATT and PGND should be

connected to as many copper planes on the

board as possible. The exposed pad should

connect to as many GND copper planes on the

board as possible, too. This improves thermal

performance because the board conducts heat

away from the IC.

3) The PCB should have a ground plane

connected directly to the return of all components

through vias (e.g. two vias per capacitor for

power stage capacitors, one via per capacitor for

small-signal components). If possible, add vias

inside the exposed pads for the IC. A star ground

design approach is typically used to keep the

circuit block currents isolated (power-signal /

control-signal), which reduces noise-coupling and

ground-bounce issues. A single ground plane for

this design gives good results.

4) Place ISET, OLIM and ILIM resistors very

close to their respective IC pins.

FREQ

VIN

VCC

ILIM

PWIN

TMR

CHG

BOOST

CSP

BATT

AGND

Figure 14: PCB Layout Guide

DESIGN EXAMPLE

Below is a design example following the

application guides for the specifications:

Table 3 Design Example

VIN

VOUT

3.7V

fSW

1200KHz

Figure 15 shows the detailed application

schematic.

The

Typical

Performance

Characteristics

section

shows

the

typical

performance and circuit waveforms. For more

possible applications of this chip, please refer to

the related Evaluation Board datasheets.

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