AD5520 datasheet(16/20 Pages) AD

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AD5520

TYPICAL APPLICATION CIRCUIT

Figure 9 shows the AD5520 as it would be used in an ATE

system. This device could be used as a per pin parametric unit

in order to speed up the rate at which testing could be done. It

could also be used as a DUT power supply, as shown in the

application circuit. The central PMU shown in the block

diagram is usually a highly accurate PMU and is shared among a

number of pins in the tester. In general, many discrete levels are

required in an ATE system for the pin drivers, comparators,

clamps, and active loads. DAC devices, such as the AD5379, offer

a highly integrated solution for a number of these levels. The

AD5379 is a dense 40-channel DAC designed with high channel

requirements, like ATE in mind.

The flexible function of the AD5520 also makes it suited for use in

instrumentation applications such as source measure units. Source

measure units are programmable instruments capable of sourcing

and measuring voltage or current simultaneously. The AD5520

provides a more integrated solution in such equipment.

EVALUATION BOARD FOR THE AD5520 PMU

A full featured evaluation kit is available for the AD5520. It

consists of an evaluation board with direct hookup via a 36-way

centronics connector to a PC. PC-based software to control the

AD5520 is provided as part of the evaluation kit. The evalua-

tion board schematic is shown in Figure 10. Note that VDD and

VSS must provide sufficient headroom for the force and measure

voltage range. In addition to the supply voltages for the evalua-

tion board, it is also necessary to provide the following voltage

levels for the clamp, comparator, and the force input pin—CLL,

CLH, CPL, CPH, and FIN. SMB connections are provided

for these voltage inputs. To use the evaluation board, it will also

be necessary to provide a DUT connected via the gold pins.

Both AGND and DGND inputs are provided on the board.

The AGND and DGND planes are connected at one location

close to the AD5520. It is recommended not to connect AGND

and DGND elsewhere in the system to avoid ground loop prob-

lems. REFGND is routed back to AGND at the power block to

maintain a clean ground reference for accurate measurements.

Each supply is decoupled to the relevant ground plane with

F and 0.1

F capacitors. The device supply pin is again

decoupled with a 10 F and 0.1 F capacitor pair to the relevant

ground plane.

Care should be taken when replacing devices to ensure that

the pins line up correctly with the PCB pads.

CENTRAL PMU

ADC

DAC

TIMING DATA

MEMORY

TIMING

GENERATOR

DLL, LOGIC

FORMATTER

DE-SKEW

DAC

VTERM

DRIVER

DAC

IOL

COMP

FORMATTER

DE-SKEW

COMPARE

MEMORY

DAC

ACTIVE LOAD

DAC

VCOM

IOH

DAC

VTH

VTL

VCL

PPMU

ADC

DAC

DEVICE POWER

SUPPLIES

ADC

DAC

GND SENSE

GUARD

AMP

COAX

RELAYS

DEVICE UNDER

TEST (DUT)

GUARD AMP

VCH

Figure 9. Typical Application ATE Circuit

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