EL5421

FN7198 Rev 2.00

Page 10 of 12

August 2, 2007

dissipation could easily increase such that the device may

be damaged. Maximum reliability is maintained if the output

continuous current never exceeds ±30mA. This limit is set by

the design of the internal metal interconnects.

Output Phase Reversal

The EL5421 is immune to phase reversal as long as the

24 shows a photo of the output of the device with the input

voltage driven beyond the supply rails. Although the device's

output will not change phase, the input's overvoltage should

be avoided. If an input voltage exceeds supply voltage by

more than 0.6V, electrostatic protection diodes placed in the

input stage of the device begin to conduct and overvoltage

damage could occur.

Power Dissipation

With the high-output drive capability of the EL5421 buffer, it

is possible to exceed the +125°C 'absolute-maximum

junction temperature' under certain load current conditions.

Therefore, it is important to calculate the maximum junction

temperature for the application to determine if load

conditions need to be modified for the buffer to remain in the

safe operating area.

The maximum power dissipation allowed in a package is

determined according to:

where:

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the loads, or:

when sourcing, and:

when sinking.

Where:

i = 1 to 4 for quad

and 26 provide a convenient way to see if the device will

overheat. The maximum safe power dissipation can be

found graphically, based on the package type and the

ambient temperature. By using the previous equation, it is a

derating curves. To ensure proper operation, it is important

to observe the recommended derating curves shown in

Figures 25 and 26.

1V

10µs

1V

FIGURE 24. OPERATION WITH BEYOND-THE-RAILS INPUT

–



JA

---------------------------------------------

=

(EQ. 1)

iV



S





–

+



=

(EQ. 2)

iV



S





–

+



=

(EQ. 3)

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1

0.9

0.6

0.4

0.3

0.2

0.1

0

0

255075

100

125

AMBIENT TEMPERATURE (°C)

85

870mW



115

°C

/W

MS

OP

10

0.8

0.5

0.7

FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE