ISL5586FCMZ datasheet(6/20 Pages) RENESAS

6 / 20 page

ISL5586

FN4924 Rev 2.00

Page 6 of 20

Nov 3, 2004

Design Equations

Refer to Figure 14 for programming resistor connections.

Loop Supervision Thresholds

SWITCH HOOK DETECT

The desired switch hook detect threshold current (ISH) is set by

a single external resistor, RSH as follows

The loop current threshold programming range is from 5mA

to 15mA.

RING TRIP DETECT

The ring trip detect threshold (IRT) is set by a single external

resistor, RRT as follows.

IRT should be set between the peak ringing current and the

peak off hook current while still ringing. In addition, the ring

trip current must be set below the transient current limit

including tolerances. The ringing signal filter capacitor CRT,

in parallel with RRT sets the ring trip response time.

LOOP CURRENT LIMIT

The DC loop current limit (ILIM) is programmed by the

external resistor RIL as follows.

The loop current limit programming range is from 15mA to

45mA.

Impedance Matching

The AC source impedance of the SLIC is programmed with

the external impedance network ZS as described next. To

synthesize and match Resistive line terminations the

programming network is simply a resistor (RS) as shown in

Figure 14. For complex line terminations such as the one

illustrated in Figure 1, a complex programming network is

required.

RESISTIVE IMPEDANCE SYNTHESIS

The AC source resistance of the SLIC is synthesized with a

single external resistor RS as follows:

The synthesized resistance (Z0) is determined by the

characteristic line resistance and protection resistors as

shown in Equation 5.

COMPLEX IMPEDANCE SYNTHESIS

A complex network is used in place of RS when the termination

impedance of the line is complex as shown in Figure 1.

The component RS has a different design equation than the

RS used for resistive impedance synthesis. The design

equations for each component are provided below where

RP1 and RP2 are the protection resistors and RP is a

component of the programming network.

VBH to 4-Wire, BSEL = 2.0V

f = 50Hz

f = 300Hz

 f 3400Hz

f = 8kHz

 f 16kHz

NOTES:

2. These parameters are controlled via design and Statistical Process Control and are not directly tested. These parameters are characterized upon

initial design release and upon design changes which would affect these characteristics.

3. Input voltage = 0.636VRMS for VBH = -100V, 0.530VRMS for VBH = -85V and 0.460VRMS for -75V devices.

4. Tested per IEEE455-1985, with 368

resistorsconnected to the Tip and Ring terminals.

5. These parameters are tested 100% at room temperature, and are guaranteed but not tested across the full temperature range via statistical

characterization and design.

6. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current limits.

7. Characterized with 2 x 10us and 10 x 1000us first level lightning surge waveform (GR-1089-CORE).

Electrical Specifications

Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V,

loop current limit = 25mA. All AC Parameters are specified at 600

, 2-wire terminating impedance over the

frequency band of 300Hz to 3.4kHz. Protection resistors = 0

. These parameters apply generically to each

product offering. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

RSH

615 ISH



(EQ. 1)

RRT

1800 IRT



(EQ. 2)

RIL

1760

ILIM

-------------

(EQ. 3)

400

----------







133.3 Z0



(EQ. 4)

RL RP1 RP2



–

(EQ. 5)

FIGURE 1. COMPLEX PROGRAMMING NETWORK

2-WIRE TERMINATION

IMPEDANCE (ZL)

PROGRAMMING

NETWORK (ZS)

133.3

R1 RP1

–

RP2

–





(EQ. 6)

133.3 R2



(EQ. 7)

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