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ISL5586FCMZ Datasheet(PDF) 19 Page - Renesas Technology Corp |
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ISL5586FCMZ Datasheet(HTML) 19 Page - Renesas Technology Corp |
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19 / 20 page ![]() ISL5586 FN4924 Rev 2.00 Page 19 of 20 Nov 3, 2004 Interface Diagram The figure 15 above shows the electrical interface between the ISL5586 and the BCM3352. Only a single channel is shown to simplify the diagram. This diagram only shows electrical interfaces and pertinent external components Receive Interface The receive interface of the BCM3352 is directly coupled to the ISL5586 differential receive input. External filter capacitors are provided to minimize noise from the BCM3352. The ISL5586 is designed with a 4-wire to 2-wire gain of +2.98dB. Transmit Interface The differential transmit output of the ISL5586 is AC coupled to an external passive network. The external passive network accomplishes many tasks. First, it filters the noise which may exist on the CMLEVEL output of the BCM3352. Second, it biases the ground referenced output signals of the ISL5586 to the CMLEVEL of the BCM3352. Lastly, the external network attenuates the signal levels coming from the ISL5586. The ISL5586 is designed with a 2-wire to 4- wire gain of 0dB and a 4-wire to 4-wire gain of +2.98dB. Ringing Interface The ISL5586 only passes the ringing signal on VRSP, VRSM to Tip and ring only during the ringing mode. Therefore, a single ringing generator as supplied by the BCM3352 drives all four sets of ringing inputs in the Broadcom reference design. The ISL5586 is designed with a differential ringing gain of 100V/V. Passive Component Values The passive component values in the Broadcom reference design may not be reflected by this document. Please refer to the Broadcom reference design documentation for the most recent schematic and COM information. TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST COMPONENT VALUE TOLERANCE RATING U1 - Ringing SLIC ISL5586 N/A N/A RTL 17.8k 1% 0.1W RRT 22.1k 1% 0.1W RSH 40k 1% 0.1W RIL 71.5k 1% 0.1W RS 66.5k 1% 0.1W RP1,RP2 0 1% 0.1W CP Not Populated 20% 10V CRT, CPOL, CSH 0.47 F 20% 10V CFB 1.0 F 20% 10V CDC 4.7 F 20% 10V CPS1 0.47 F 20% >100V CPS2, CPS3 0.1 F 20% 100V CT1, CT2 4.7 F CR1, CR2, CR3 3300pF CX1, CX2, CX3 150pF D1 1N400X Type with Breakdown > 100V. D2,D3 1N4935 Type RP1, RP2 Protection resistor values are application dependent and will be determined by protection requirements. Standard applications will use 49 per side. Design Parameters: Ring Trip Threshold = 81mAPEAK, Switch Hook Threshold = 15mA, Loop Current Limit = 24.6mA, Synthesize Device Impedance = (3*66.5k /400 = 498.8, protection resistors = 50, impedance across Tip and Ring terminals = 599. Transient current limit = 100mA. |
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