8

ATSAM2133B

2694A–DRMSD–05/03

100-ball LFBGA Package

Table 3. Pin by Function - 100-ball LFBGA Package

Pin Name

Pin Number

Type

Function

GND

A3, A9, C7, D5,

D10, E1, F7, G4,

G5, J5, J8

PWR

Power ground - all GND pins should be returned to digital ground

VC2

B6, C5, C6, E2, H6

PWR

Core power +2.5V ±10%. All V

switch is used for minimum power-down consumption, then all these pins should be

connected to PWROUT, the output of the built-in power switch.

VC3

C3, D8, G2, G10,

H4, H7

PWR

Periphery power 2.25V to 3.7V. All V

should be lower than V

PWRIN

A8

PWR

Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this

pin must be connected to nominal 2.5V

PWROUT

B7

PWR

Power switch output. Use this pin to supply 2.5V core power by connecting it to all V

C2

pins.

D0 - D7

E4, D1, E3, F4, F3,

F5, F2, F1

I/O

8-bit data bus to host processor. Information on these pins is parallel MIDI (MPU-401

type applications).

CS

C1

IN

Chip select from host, active low.

WR

C2

IN

Write from host, active low.

RD

D2

IN

Read from host, active low.

A0

D3

IN

Selects MPU-401 internal registers:

0: data registers (read/write)

1: status register (read) control register (write)

IRQ

B1

TSOUT

Tri-state output pin, active high.

RESET

H3

IN

Master reset input, active low.

X1, X2

D6, A7

-

Crystal connection. Crystal frequency should be Fs * 256 (typ 11.2896 MHz). Crystal

frequency is internally multiplied by 4 to provide the IC master clock. An external

11.2896 MHz clock can also be used on X1 (2.5V

cannot be used to drive external ICs; use CKOUT instead.

CKOUT

E5

OUT

Buffered X2 output. Can be used to drive external DAC master clock (256 * Fs)

DABD0 - 1

A4, B4

OUT

Two stereo serial audio data output (4 audio channels). Each output holds 64 bits

(2 x 32) of serial data per frame. Audio data precise up to 20 bits. DABD0 can hold

additional control data (mute, A/D gain, D/A gain, etc.)

CLBD

C4

OUT

Audio data bit clock, provides timing to DABD0 - 1, DAAD.

WSBD

B3

OUT

Audio data word select. The timing of WSBD can be selected to be I2S or Japanese

compatible.

DAAD

A2

IN

Stereo serial audio data input.

P0 - P3

G1, G3, H2, H1

I/O

General-purpose programmable I/O pins.

DBCLK

A5

IN

Debug clock. Should be connected to V

low just after RESET, then the internal ROM debugger/flash programmer is started

DBDATA

D4

I/O

Debug data. Allows serial communication for debug/flash programming

DBACK

B5

OUT

Debug ack. Toggled each time a bit is received/sent on DBDATA

MIDI IN

A1

IN

MIDI IN input

MIDI OUT

B2

OUT

MIDI OUT output