3

ATSAM2133B

2694A–DRMSD–05/03

General Description

Block Diagram

Synthesis/DSP Engine

The synthesis/DSP engine operates on a frame timing basis with the frame subdivided

into 64 process slots. Each process is, in turn, divided into 16 micro-instructions known

as algorithms. Up to 32 synthesis/DSP algorithms can be stored on-chip in the Alg RAM

memory, allowing the device to be programmed for a number of audio signal genera-

tion/processing applications. The synthesis/DSP engine is capable of generating 64

simultaneous voices using algorithms such as wavetable synthesis with interpolation,

alternate loop and 24 dB resonant filtering for each voice. Slots may be linked together

(ML RAM) to allow implementation of more complex synthesis algorithms.

A typical application will use half the capacity of the synthesis/DSP engine for synthesis,

thus providing state-of-the-art 32-voice wavetable polyphony. The remaining processing

power will be used for typical functions such as reverberation, chorus, audio-in process-

ing, surround effect, equalizer, etc.

Frequently-accessed synthesis/DSP parameter data are stored in five banks of on-chip

RAM memory. Sample data or delay lines, which are accessed relatively infrequently,

are stored in external ROM or internal 32K x 16 RAM memory. The combination of local-

ized micro-program memory and localized parameter data allows micro-instructions to

execute in 20 ns (50 MIPS). Separate buses from each of the on-chip parameter RAM

memory banks allow highly parallel data movement to increase the effectiveness of

each micro-instruction. With this architecture, a single micro-instruction can accomplish

up to six simultaneous operations (add, multiply, load, store, etc.), providing a potential

throughput of 300 million operations per second (MOPS).

ATSAM2133B

P16 Processor

16-bit CISC

Processor Core

includes

256 x 16 Data RAM

Synthesis/DSP

64-slot RISC DSP Core

includes

512 x 32 Alg RAM

128 x 28 MA1 RAM

256 x 28 MA2 RAM

256 x 28 MB RAM

256 x 16 MX RAM

256 x 12 MY RAM

64 x 13 ML RAM

32K x 16 RAM

MMU

Memory

Management

Unit

ROM

Debug/Flash Prog

I/O Functions

includes

Control/Status

MIDI UART

Timers

Codec Data I/F

Host I/F FIFO

MIDI

MPU

Debug/Flash

Prog

ROM

or

Flash

Codec + DAC