5

ATSAM2133B

2694A–DRMSD–05/03

Pin Description

100-lead TQFP Package

Table 1. Pin by Function - 100-lead TQFP Package

Pin Name

Pin Number

Type

Function

GND

10, 16, 31, 36,

45, 56, 68, 76,

80, 84, 96

PWR

Power ground - all GND pins should be returned to digital ground.

VC2

11, 37, 83, 86,

87

PWR

Core power +2.5V ±10%. All V

switch is used for minimum power down consumption, then all these pins should be

connected to PWROUT, the output of the built-in power switch.

VC3

17, 30, 44, 57,

69, 97

PWR

Periphery power +2.25V to 3.7V. All V

should not be lower than V

PWRIN

77

PWR

Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this pin

must be connected to nominal 2.5V.

PWROUT

78

PWR

Power switch output. Use this pin to supply 2.5V core power by connecting it to all V

D0 - D7

6-9, 12-15

I/O

8-bit data bus to host processor. Information on these pins is parallel MIDI (MPU-401 type

applications)

CS

2

IN

Chip select from host, active low.

WR

4

IN

Write from host, active low.

RD

3

IN

Read from host, active low.

A0

5

IN

Selects MPU-401 internal registers:

0 = data registers (read/write)

1 = status register (read) control register (write)

IRQ

1

TSOUT

Tri-state output pin, active high.

RESET

22

IN

Master reset input, active low.

X1, X2

81, 82

-

Crystal connection. Crystal frequency should be Fs*256 (typ 11.2896 MHz). Crystal

frequency is internally multiplied by 4 to provide the IC master clock. An external 11.2896

MHz clock can also be used on X1 (2.5V

used to drive external ICs; use CKOUT instead.

CKOUT

88

OUT

Buffered X2 output, can be used to drive external DAC master clock (256 * Fs)

DABD0 -1

93, 92

OUT

Two stereo serial audio data output (4 audio channels). Each output holds 64 bits (2 x 32)

of serial data per frame. Audio data has up to 20 bits precision. DABD0 can hold additional

control data (mute, A/D gain, D/A gain, etc.)

CLBD

94

OUT

Audio data bit clock, provides timing to DABD0 - 1, DAAD.

WSBD

95

OUT

compatible.

DAAD

98

IN

Stereo serial audio data input.

P0 - P3

18 - 21

I/O

General-purpose programmable I/O pins.

DBCLK

90

IN

Debug clock. Should be connected to V

just after RESET, then the internal ROM debugger/flash programmer is started.

DBDATA

91

I/O

Debug data. Allows serial communication for debug/flash programming.

DBACK

89

OUT

Debug acknowledge. Toggled each time a bit is received/sent on DBDATA.