AD8115ASTZ datasheet(19/25 Pages) AD

19 / 25 page

Data Sheet

AD8114/AD8115

Rev. C | Page 19 of 25

One important consideration in using parallel programming is

that the RESET signal does not reset all registers in the AD8114/

AD8115. When taken low, the RESET signal only sets each output

to the disabled state. This is helpful during power-up to ensure

that two parallel outputs are not active at the same time.

After initial power-up, the internal registers in the device generally

have random data, even though the RESET signal was asserted.

If parallel programming is used to program one output, then

that output is properly programmed, but the rest of the device

has a random program state depending on the internal register

content at power-up. Therefore, when using parallel programming,

it is essential that all outputs be programmed to a desired state

after power-up. This ensures that the programming matrix is

always in a known state. From then on, parallel programming

can be used to modify a single output or more at a time.

In similar fashion, if both CE and UPDATE are taken low after

initial power-up, the random power-up data in the shift register

is programmed into the matrix. Therefore, to prevent the

crosspoint from being programmed into an unknown state, do

not apply low logic levels to both CE and UPDATE after power

is initially applied. Programming the full shift register one time

to a desired state by either serial or parallel programming after

initial power-up eliminates the possibility of programming the

matrix to an unknown state.

To change the programming of an output via parallel

programming, SER/PAR and UPDATE should be taken high

and CE should be taken low. The CLK signal should be in the

high state. The 4-bit address of the output to be programmed

should be put on A0 to A3. The first four data bits (D0 to D3)

should contain the information that identifies the input that

gets programmed to the output that is addressed. The fourth

data bit (D4) determines the enabled state of the output. If D4 is

low (output disabled), then the data on D0 to D3 does not matter.

After the desired address and data signals have been established,

they can be latched into the shift register by a high to low transition

of the CLK signal. The matrix is not programmed, however, until

the UPDATE signal is taken low. It is thus possible to latch in

new data for several or all of the outputs first via successive

negative transitions of CLK while UPDATE is held high, and

then have all the new data take effect when UPDATE goes low.

This technique should be used when programming the device

for the first time after power-up when using parallel programming.

POWER-ON RESET

When powering up the AD8114/AD8115, it is usually desirable

to have the outputs come up in the disabled state. When taken

low, the RESET pin causes all outputs to be in the disabled state.

However, the RESET signal does not reset all registers in the

AD8114/AD8115. This is important when operating in the

parallel programming mode.

Please refer to that section for information about programming

internal registers after power-up. Serial programming programs

the entire matrix each time, so no special considerations apply.

Since the data in the shift register is random after power-up, it

should not be used to program the matrix, or the matrix can

enter unknown states. To prevent this, do not apply logic low

signals to both CE and UPDATE initially after power-up. The

shift register should first be loaded with the desired data, and

then UPDATE can be taken low to program the device.

The RESET pin has a 20 kΩ pull-up resistor to DVDD that can

be used to create a simple power-up reset circuit. A capacitor

from RESET to ground holds RESET low for some time while

the rest of the device stabilizes. The low condition causes all the

outputs to be disabled. The capacitor then charges through the

pull-up resistor to the high state, thus allowing full programming

capability of the device.

GAIN SELECTION

The 16 × 16 crosspoints come in two versions, depending on

the gain of the analog circuit paths that is desired. The AD8114

device is unity gain and can be used for analog logic switching

and other applications where unity gain is desired. The AD8114

can also be used for the input and interior sections of larger

crosspoint arrays where termination of output signals is not

usually used. The AD8114 outputs have very high impedance

when their outputs are disabled.

The AD8115 can be used for devices that are used to drive a

terminated cable with its outputs. This device has a built-in gain

of 2 that eliminates the need for a gain-of-2 buffer to drive a

video line. Its high output disabled impedance minimizes

signal degradation when paralleling additional outputs.

CREATING LARGER CROSSPOINT ARRAYS

The AD8114/AD8115 are high density building blocks for

creating crosspoint arrays of dimensions larger than 16 × 16.

Various features, such as output disable, chip enable, and gain-

of-1 and gain-of-2 options, are useful for creating larger arrays.

When required for customizing a crosspoint array size, they can

be used with the AD8108 and AD8109, a pair of (unity gain and

gain-of-2) 8 × 8 video crosspoint switches, or with the AD8110

and AD8111, a pair of (unity gain and gain-of-2) 16 × 8 video

crosspoint switches.

The first consideration in constructing a larger crosspoint is to

determine the minimum number of devices required. The 16 ×

16 architecture of the AD8114/AD8115 contains 256 points, which

is a factor of 64 greater than a 4 × 1 crosspoint (or multiplexer).

The printed circuit board area, power consumption, and design

effort savings are readily apparent when compared to using

these smaller devices.

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