1

FB

PD

8

2

NC

7

VS+

3

IN±

6

OUT

4

IN+

5

VS±

+

±

VS+

VSí

VIN+

VOUT

Power Supply

ESD Cell

VINí

FB

10

OPA855

SBOS622 – JULY 2018

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9.3 Feature Description

9.3.1 Input and ESD Protection

The OPA855 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown

voltages are low for these small geometry devices, and as a result, all device pins are protected with internal

ESD protection diodes to the power supplies as Figure 6 shows. There are two antiparallel diodes between the

inputs of the amplifier that clamp the inputs during an overrange or fault condition.

Figure 6. Internal ESD Structure

9.3.2 Feedback Pin

The OPA855 pin layout is optimized to minimize parasitic inductance and capacitance, which is critical in high-

speed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The FB pin is

separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin must be

left floating. There are two advantages to this pin layout:

Figure 7) rather than going around the package.

2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins.