ADV7482

Data Sheet

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

I2S_SCLK High Time

45

55

% duty

cycle

I2S_SCLK Low Time

45

55

% duty

cycle

I2S_LRCLK Data Transition Time

End of valid data to I2S_SCLK falling edge

10

ns

I2S_SCLK falling edge to start of valid data

10

ns

I2S_SDATA Data Transition Time

End of valid data to I2S_SCLK falling edge

5

ns

I2S_SCLK falling edge to start of valid data

5

ns

1

Required by design.

2

The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.

3

Guaranteed by design.

4

These specifications only apply when the LLC_DLL_PHASE[4:0] (IO Map, Register 0x0C[4:0]) is set to 00000.

5

Guaranteed by lab characterization.

Timing Diagrams

Figure 4. 8-Bit Digital Pixel Video Input, SDR Video Data Timing

Figure 5. 8-Bit Digital Pixel Video Input, DDR Video Data Timing

Figure 6. 8-Bit Digital Pixel Video Output, SDR Video Data Timing

SDATA

SCLK

LLC

P7 TO P0

LLC

P7 TO P0

LLC

P7 TO P0

Rev. 0 | Page 10 of 20