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ADV7482WBBCZ Datasheet(PDF) 18 Page - Analog Devices |
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ADV7482WBBCZ Datasheet(HTML) 18 Page - Analog Devices |
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18 / 20 page ![]() ADV7482 Data Sheet Figure 13. Typical Fully Differential Input Resistor Divider Network The ADC features three clocking rates that allow 4× oversampling per channel for CVBS mode, Y/C mode, and YPbPr mode. The fully differential AFE of the ADV7482 provides inherent small and large signal noise rejection, improved electromagnetic interference (EMI) protection, and the ability to absorb ground bounce. Support is provided for both true differential and pseudo differential signals. The main AFE features include • A single 172 MHz, 10-bit ADC that enables true 8-bit video decoding. • 8-channel analog input mux that enables multiple source connections without the requirement of an external mux. • A current clamp control loop that ensures that any dc offsets are removed from the video signal entering the SDP. • Diagnostic capability on all differential inputs. • Support for 4 V common-mode input range. • Support for analog input signals up to 1 V p-p. • Support for single-ended, pseudo differential, and fully differential inputs. SHORT TO BATTERY DIAGNOSTICS In differential mode, the ADV7482 is protected against STB events by ac coupling capacitors (see Figure 12 and Figure 13). The input network resistors are sized to reduce the current flow during an STB event, thus preventing damage to the resistors. Note that the input network resistors and the ac coupling capacitors must be chosen with ratings guaranteeing they are able to withstand the high voltage of STB events. The four diagnostic inputs of the ADV7482 provide diagnostic capability for all differential inputs. The ADV7482 can detect an STB event on either the positive or the negative composite input and trigger an interrupt. The 75 Ω (pseudo differential) or 150 Ω (fully differential) parallel termination resistor enables one DIAGx pin to sense an STB event on either input, because there is a minimal voltage drop across the resistor. Figure 14. Diagnostic Connection for Differential Inputs Resistors R4 and R5 divide down the voltage at the input connector to protect the DIAGx pin from an STB event. The DIAGx pin circuitry compares this voltage to a programmable reference voltage, known as the diagnostic slice level. When the diagnostic slice level is exceeded, an STB event has occurred. R4 and R5 are sized to allow the use of low cost, small footprint resistors that are tolerant of STB events. Use the following equation to find the STB voltage for a selected diagnostic slice level. EL _SLICE_LEV DIAGNOSTIC R5 R4 R5 V R STB_TRIGGE × + = where: VSTB_TRIGGER is the minimum voltage required at the input connector to trigger the STB interrupt on the ADV7482. DIAGNOSTIC_SLICE_LEVEL is the programmable reference voltage. For example, with a diagnostic slice level programmed to 1.125 V, an R4 value of 9.1 kΩ, and an R5 value of 1 kΩ, the minimum voltage required at the input connector to trigger the STB interrupt is approximately 11.4 V. When the DIAGx pin voltage exceeds the diagnostic slice level voltage, a hardware interrupt is triggered and indicated by one of the interrupt pins. A readback register specifies the input on which the STB event occurred. STANDARD DEFINITION PROCESSOR The ADV7482 is capable of decoding a large selection of baseband video signals in composite (both single-ended and differential), S-Video, and component formats. The video standards supported by the video processor include • PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N, PAL Nc, and PAL 60 • NTSC J, NTSC M, and NTSC 4.43 • SECAM B, SECAM D, SECAM G, SECAM K, and SECAM L The ADV7482 can automatically detect the video standard and process it accordingly. The ADV7482 has a five-line adaptive 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the AINx AINy ANALOG INPUT ANALOG INPUT CVBS_P CVBS_N 1.3kΩ 1.3kΩ 150Ω 430Ω 430Ω 100nF 100nF AINx AINy ANALOG INPUT ANALOG INPUT CVBS_P CVBS_N 1.3k Ω 1.3k Ω 75 Ω OR 150 Ω 430 Ω 430 Ω DIAGx R4 R5 100nF 100nF Rev. 0 | Page 18 of 20 |
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