ADV7482WBBCZ datasheet(19/20 Pages) AD

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Data Sheet

ADV7482

video standard and signal quality without requiring user

intervention. Video user controls such as brightness, contrast,

saturation, and hue are also available with the ADV7482.

The ADV7482 implements the patented Adaptive Digital Line

Length Tracking (ADLLT™) algorithm to track varying video

line lengths from sources such as a VCR. ADLLT enables the

ADV7482 to track and decode poor quality video sources such

as VCRs and noisy sources from tuner outputs, VCD players,

and camcorders. The ADV7482 contains a chroma transient

improvement (CTI) processor that sharpens the edge rate of

chroma transitions, resulting in sharper vertical transitions.

The ACE of the ADV7482 offers improved visual detail using

an algorithm that automatically varies contrast levels to enhance

picture detail. ACE allows the contrast of an image to increase

depending on the content of the picture. Typically, this allows

bright areas to be made brighter and dark areas to be made

darker. However, the ADV7482 ACE feature also allows the

contrast within dark areas to increase without significantly

affecting the bright areas of the picture. This feature is

particularly useful in automotive applications, where it is

important to discern objects in shaded areas.

Down dithering converts the output of the ADV7482 from an

8-bit to a 6-bit output, enabling ease of design for standard LCD

panels.

The SDP can process a variety of VBI data services, such as

closed captioning (CCAP), wide screen signaling (WSS), and

copy generation management system (CGMS).

The ADV7482 is fully Rovi®(Macrovision®) compliant; detection

circuitry enables Type I, Type II, and Type III protection levels

to be identified and reported to the user. The decoder is also

fully robust to all Macrovision signal inputs.

8-BIT DIGITAL INPUT/OUTPUT PORT

The ADV7482 features an 8-bit digital bidirectional port. The

following formats are supported both as input and output ports:

•

8-bit interleaved 4:2:2 SDR input/output with embedded

timing codes

•

8-bit interleaved 4:2:2 DDR input/output with embedded

timing codes

The maximum input and output video resolution supported is

720p/1080i in both SDR and DDR modes.

Video received on the 8-bit digital input port can be routed to

the four-lane MIPI CSI-2 transmitter. Video sent on the 8-bit

digital output port can be routed from either the SD core or the

CP core.

AUDIO PROCESSING

The ADV7482 features an audio processor that handles the

audio extracted from the HDMI stream by the HDMI receiver.

It contains an audio mute controller that can detect a variety of

conditions that may result in audible extraneous noise in the

audio output. On detection of these conditions, a 2-channel

linear PCM audio signal can be ramped down to a mute state to

prevent audio clicks or pops.

The audio is output on a single flexible serial digital audio

output port supporting I2S-compatible, left justified, and right

justified audio output modes in master mode only. TDM is also

supported, allowing up to eight audio channels with a sample

rate up to 48 kHz to be transmitted over the single serial digital

audio interface.

MIPI CSI-2 TRANSMITTERS

The ADV7482 features two MIPI CSI-2 transmitters: a four-

lane transmitter (Transmitter A) and a single lane transmitter

(Transmitter B).

The four-lane transmitter consists of four differential data lanes

(DA0N, DA0P, DA1N, DA1P, DA2N, DA2P, DA3N and DA3P),

and a differential clock lane (CLKAN and CLKAP). It supports

four data lanes, two data lanes, and one data lane muxing

options, and can be used to transmit video received on either

the HDMI receiver (processed through the CP), the 8-bit digital

input port, or the AFE (processed through the SDP).

The main features of the four-lane MIPI transmitter

(Transmitter A) include

•

Support for 8-bit and 10-bit YCbCr 4:2:2 video modes.

•

Support for 24-bit RGB 4:4:4 (RGB888), 18-bit RGB 4:4:4

(RGB666), and 16-bit RGB 4:4:4 (RGB565) video modes.

•

Support for video formats ranging from 480i to 1080p, and

display resolutions from VGA to UXGA (certain

restrictions apply to the muxing option, video mode, and

video format that can be selected).

•

Data lanes and clock lane remapping to ease PCB layout.

The single lane transmitter consists of a single differential data

lane (DB0N and DB0P) and a differential clock lane (CLKBN

and CLKBP). It transmits video received on the AFE (processed

through the SDP).

The main features of the single lane MIPI transmitter

(Transmitter B) include

•

Support for 8-bit YCbCr 4:2:2 video mode.

•

Support for 480i and 576i video formats.

INTERRUPTS

The ADV7482 features two interrupt request pins. INTRQ1 and

INTRQ2 can be programmed to trigger interrupts based on

various selectable events related to the HDMI receiver (video

and audio related), the SDP, and the CP.

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