Data Sheet

ADV7630

Rev. 0 | Page 11 of 16

Pin No.

Mnemonic

Type

Description

35

TXA_DDC_SDA

Digital

input/output

HDCP Master Serial Data of HDMI Output Port A. TXA_DDC_SDA is a 3.3 V open-drain

input/output that is 5 V tolerant.

36

TXA_DDC_SCL

Digital output

HDCP Master Serial Clock of HDMI Output Port A. TXA_DDC_SCL is a 3.3 V open-drain

output that is 5 V tolerant.

37

DVDD

Power

Digital Core Supply Voltage (1.8 V).

38

TXA_PVDD

Power

1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It

should be kept separately from TXB_PVDD to avoid possible crosstalk. This power

supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with

10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the

package.

39

TXA_PVDD

Power

1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It

should be kept separately from TXB_PVDD to avoid possible crosstalk. This power

supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with

10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the

package.

41

TXA_PVDD

Power

1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It

should be kept separately from TXB_PVDD to avoid possible crosstalk. This power

supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with

10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the

package.

42

R_EXT

Input

Sets internal reference currents. Place a 470 Ω resistor (1% tolerance) between this pin

and ground.

43

TX_AVDD

Power

1.8 V Power Supply for TMDS Outputs.

44

TXA_C−

HDMI output

TMDS Clock Output Complement of HDMI Output Port A.

45

TXA_C+

HDMI output

TMDS Clock Output True of HDMI Output Port A.

46

TX_AVDD

Power

1.8 V Power Supply for TMDS Outputs.

47

TXA_0−

HDMI output

TMDS Output Channel 0 Complement of HDMI Output Port A.

48

TXA_0+

HDMI output

TMDS Output Channel 0 True of HDMI Output Port A.

49

TX_AVDD

Power

1.8 V Power Supply for TMDS Outputs.

50

TXA_1−

HDMI output

TMDS Output Channel 1 Complement of HDMI Output Port A.

51

TXA_1+

HDMI output

TMDS Output Channel 1 True of HDMI Output Port A.

52

TXA_2−

HDMI output

TMDS Output Channel 2 Complement of HDMI Output Port A.

53

TXA_2+

HDMI output

TMDS Output Channel 2 True of HDMI Output Port A.

54

TX_AVDD

Power

1.8 V Power Supply for TMDS Outputs.

56

TXA_HPD

Digital input

Hot Plug Detect Signal of HDMI Output Port A. This pin indicates to the interface

whether the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels.

57

DDCD_SCL

Digital input

HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant.

58

DDCD_SDA

Digital

input/output

HDCP Slave Serial Data Port D. DDCD_SDA is a 5 V tolerant 3.3 V input and open-drain

output.

59

DDCC_SCL

Digital input

HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.

60

DDCC_SDA

Digital

input/output

HDCP Slave Serial Data Port C. DDCC_SDA is a 5 V tolerant 3.3 V input and open-drain

output.

61

DDCB_SCL

Digital input

HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.

62

DDCB_SDA

Digital

input/output

HDCP Slave Serial Data Port B. DDCB_SDA is a 5 V tolerant 3.3 V input and open-drain

output.

63

DDCA_SCL

Digital input

HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.

64

DDCA_SDA

Digital

input/output

HDCP Slave Serial Data Port A. DDCA_SDA is a 5 V tolerant 3.3 V input and open-drain

output.

65

REG_3P3V

Power output

Output of Internal 3.3 V LDO. Must be connected to ground via decoupling capacitors

(10 nF in parallel with 100 nF capacitor). This pin can be used to power up external

EDID SPI EEPROM when part is in power-down mode and 5 V is connected to the part

from an HDMI cable.

66

EP_MOSI

Digital output

SPI Master Output/Slave Input for External EDID Interface.

67

EP_MISO

Digital input

SPI Master Input/Slave Output for External EDID Interface.

68

EP_SCK

Digital output

SPI Clock for External EDID Interface.

69

EP_CS

Digital output

SPI Chip Select for External EDID Interface.