LPC804 datasheet(67/81 Pages) NXP

67 / 81 page

LPC804

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 23 March 2018

67 of 81

NXP Semiconductors

LPC804

32-bit Arm Cortex-M0+ microcontroller

(1) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the VDD pin. Add one set of decoupling

capacitors to each VDD pin.

(2) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and VDD pins. The 10 μF bypass capacitor

filters the power line. Tie VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used.

(3) Uses the Arm 10-pin interface for SWD.

(4) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 4.

(5) External pull-up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull-up enabled by

default.

Fig 33. Power, clock, and debug connections

PIO0_12

ADC_0

VDD

VREFP

PIO0_7/ADC_1/ACMPVREF

LPC804

3.3 V

(4) (ADC_1),

(2) (ACMPVREF)

GND

(1)

(4)

(2)

0.01 μF

0.1 μF

3.3 V

GND

10 μF

0.1 μF

ISP select pin

aaa-029252

SWDIO/PIO0_2

SWCLK/PIO0_3

RESETN/PIO0_5

VSS

3.3 V

GND

n.c.

SWD connector

(5)

(4)

(5)

3.3 V

~10 kΩ - 100 kΩ

3.3 V

LPC804 Datasheet(PDF) 67 Page - NXP Semiconductors

LPC804 Datasheet(HTML) 67 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Download

Link URL