LPC804 datasheet(77/81 Pages) NXP

77 / 81 page

LPC804

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Product data sheet

Rev. 1.3 — 23 March 2018

77 of 81

NXP Semiconductors

LPC804

32-bit Arm Cortex-M0+ microcontroller

20. Revision history

Table 35.

Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC804 v.1.3

20180323

Product data sheet

LPC804 v.1.2

Modifications:

• Fixed revision number.

• Updated Table 15 “Flash characteristics”. ter consolidated to tprog/ter.

• Updated Section 9.25.4.4 “Deep power-down mode” with text: Five general-purpose

registers are available to store information during deep power-down mode.

LPC804 v.1.2

20180227

Product data sheet

LPC804 v.1.1

Modifications:

• Updated Table 12 “Static characteristics, supply pins”: Added condition:

system clock = 1 MHz, VDD = 3.3 V.

• Updated Table 16 “Dynamic characteristic: FRO”: Max values: FRO clock frequency;

Condition:

20 C  Tamb  70 C and FRO clock frequency; Condition: 40 C  Tamb

 105 C.

• Updated title of Section 13.1 “Flash memory (EEPROM based)”.

LPC804 v.1.1

20180214

Product data sheet

LPC804 v.1

Modifications:

• Updated Section 2 “Features and benefits”.

• Updated Table 5 “Movable functions (assign to pins PIO0_0 to PIO0_5, PIO0_7 to

PIO0_30 through switch matrix)”.

• Added level shifter functionality to Section 9.8 “I/O configuration”.

• Updated Table 16 “Dynamic characteristic: FRO”: Changed frequencies to 9 MHz, 12

MHz, and 15 MHz. Added Condition:

20 C  Tamb  70 C and Condition: 40 C 

Tamb  70 C.

LPC804 v.1

20180126

Product data sheet

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