AD9576BCPZ datasheet(44/65 Pages) AD

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AD9576

Data Sheet

Rev. A | Page 44 of 65

DON'T CARE

A14

A13

A12

A11

A10

A9A8A7

A6A5D4D3

D2D1D0

DON'T CARE

R/W

tDS

tDH

tHIGH

tLOW

tSCLK

SCLK

SDIO

Figure 29. Timing Diagram for Serial Control Port Write—MSB First

SCLK

DATA BIT N

DATA BIT N – 1

tDV

SDIO

Figure 30. Timing Diagram for Serial Control Port Register Read—MSB First

SCLK DON'T CARE

DON'T CARE

16-BIT INSTRUCTION HEADER

SDIO

DON'T CARE

A0 A1

A9 A10 A11 A12

R/W

A14

A13

D5 D6

Figure 31. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data

SCLK

SDIO

tHIGH

tLOW

tSCLK

tDS

tDH

BIT N

BIT N + 1

Figure 32. Timing Diagram for Serial Control Port—Write

I2C SERIAL PORT OPERATION

The I2C interface is popular because it requires only two pins

and easily supports multiple devices on the same bus. Its main

disadvantage is programming speed, which is 400 kbps maximum.

The AD9576 I2C port design uses the I2C fast mode; however, it

supports both the 100 kHz standard mode and 400 kHz fast mode.

The AD9576 does not strictly adhere to every requirement in

the original I2C specification. In particular, specifications such

as slew rate limiting and glitch filtering are not implemented.

Therefore, the AD9576 is I2C-compatible, but may not be fully

I2C compliant.

The AD9576 I2C port consists of a serial data line (SDA) and a

serial clock line (SCL). In an I2C bus system, the AD9576 is

connected to the serial bus (data bus SDA and clock bus SCL) as

a slave device; that is, no clock is generated by the AD9576. The

AD9576 uses direct 16-bit memory addressing instead of more

common 8-bit memory addressing.

The AD9576 allows up to seven unique slave devices to occupy

the I2C bus. These are accessed via a 7-bit slave address

transmitted as part of an I2C packet. Only the device with a

matching slave address responds to subsequent I2C commands.

Table 35 lists the supported device slave addresses.

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