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AD9576BCPZ Datasheet(PDF) 58 Page - Analog Devices

Part # AD9576BCPZ
Description  Dual PLL, Asynchronous Clock Generator
PDF  65 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9576BCPZ Datasheet(HTML) 58 Page - Analog Devices

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AD9576
Data Sheet
Rev. A | Page 58 of 65
PLL0 DISTRIBUTION REGISTERS (REGISTER 0x140 TO REGISTER 0x14D)
Table 49. PLL0 Distribution Registers
Address
Bits
Bit Name
Settings
Description
Reset
Access
0x140
7
Reserved
Reserved.
0x0
R
6
Q0 power-down
Divider power-down control.
0x0
R/W
0
Normal operation.
1
Powered down.
[5:0]
Q0 divider ratio
These bits set the operating divide ratio. Divide ratio = bit field value + 1.
0x3
R/W
0x141
[7:6]
Reserved
Reserved.
0x0
R
[5:0]
Q0 initial phase
These bits set the divider static phase offset. The phase offset is in
units of half cycles of the input clock.
0x0
R/W
0x142
[7:3]
Reserved
Reserved.
0x0
R
2
OUT0 power-down
Driver power-down control.
0x0
R/W
0
Normal operation.
1
Powered down.
[1:0]
OUT0 driver format
These bits select the driver format of OUT0.
0x0
R/W
00
LVDS, 3.5 mA.
01
LVDS, 4.2 mA.
10
HSTL, 8 mA.
11
1.8 V CMOS.
0x143
[7:3]
Reserved
Reserved.
0x0
R
2
OUT1 power-down
Driver power-down control.
0x0
R/W
0
Normal operation.
1
Powered down.
[1:0]
OUT1 driver format
These bits select the driver format of OUT1.
0x0
R/W
00
LVDS, 3.5 mA.
01
LVDS, 4.2 mA.
10
HSTL, 8 mA.
11
1.8 V CMOS.
0x144
[7:3]
Reserved
Reserved.
0x0
R
2
OUT2 power-down
Driver power-down control.
0x0
R/W
0
Normal operation.
1
Powered down.
[1:0]
OUT2 driver format
These bits select the driver format of OUT2.
0x0
R/W
00
LVDS, 3.5 mA.
01
LVDS, 4.2 mA.
10
HSTL, 8 mA.
11
1.8 V CMOS.
0x145
[7:3]
Reserved
Reserved.
0x0
R
2
OUT3 power-down
Driver power-down control.
0x0
R/W
0
Normal operation.
1
Powered down.
[1:0]
OUT3 driver format
These bits select the driver format of OUT3.
0x0
R/W
00
LVDS 3.5 mA.
01
LVDS 4.2 mA.
10
HSTL 8 mA.
11
1.8 V CMOS.
0x146
7
Reserved
Reserved.
0x0
R
6
Q1 power-down
Divider power-down control.
0x0
R/W
0
Normal operation.
1
Powered down.
[5:0]
Q1 divide ratio
These bits set the operating divide ratio. Divide ratio = bit field value + 1.
0x3
R/W



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