AD9576BCPZ datasheet(13/65 Pages) AD

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Data Sheet

AD9576

Rev. A | Page 13 of 65

PLL1 AND BYPASS CHANNEL ABSOLUTE CLOCK JITTER SPECIFICATIONS

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HSTL INTEGRATED RMS JITTER

25 MHz Output

0.125

Source = 25 MHz Taitien XTAL; jitter integration bandwidth =

12 kHz to 5 MHz

100 MHz Output

1.605

Source = PLL1; Qx divider = 8; jitter integration bandwidth =

12 kHz to 20 MHz

400 MHz Output

1.641

Source = PLL1; Qx divider = 2; jitter integration bandwidth =

12 kHz to 20 MHz

HCSL INTEGRATED RMS JITTER

25 MHz Output

0.287

Source = 25 MHz Taitien XTAL; jitter integration bandwidth =

12 kHz to 5 MHz

100 MHz Output

1.54

Source = PLL1; Qx divider = 8; jitter integration bandwidth =

12 kHz to 20 MHz

400 MHz Output

1.617

Source = PLL1; Qx divider = 2; jitter integration bandwidth =

12 kHz to 20 MHz

LVDS INTEGRATED RMS JITTER

25 MHz Output

0.535

Source = 25 MHz Taitien XTAL; jitter integration bandwidth =

12 kHz to 5 MHz

100 MHz Output

1.535

Source = PLL1; Qx divider = 8; jitter integration bandwidth =

12 kHz to 20 MHz

400 MHz Output

1.605

Source = PLL1; Qx divider = 2; jitter integration bandwidth =

12 kHz to 20 MHz

2.5 V CMOS INTEGRATED RMS JITTER

25 MHz Output

0.17

Source = 25 MHz Taitien XTAL; jitter integration bandwidth =

12 kHz to 5 MHz

100 MHz Output

1.669

Source = PLL1; Qx divider = 8; jitter integration bandwidth =

12 kHz to 20 MHz

400 MHz Output

1.586

Source = PLL1; Qx divider = 2; jitter integration bandwidth =

12 kHz to 20 MHz

OUT8 TO OUT10 CHANNEL CYCLE TO CYCLE CLOCK JITTER SPECIFICATIONS

Frequency multiplier (×2) at PLL input enabled. Cycle to cycle jitter magnitude varies with respect to the clock edge (rising or falling).

Table 12 indicates jitter for the worst edge (rising or falling). The better edge typically offers a factor of 2 improvement over the tabulated jitter.

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVDS CYCLE TO CYCLE JITTER

Peak-to-peak jitter, 10,000 cycles

66.6 MHz Output

43.9

133.3 MHz Output

30.3

1.8 V CMOS CYCLE TO CYCLE JITTER

Peak-to-peak jitter, 10,000 cycles

66.6 MHz Output

35.3

133.3 MHz Output

27.4

3.3 V CMOS CYCLE TO CYCLE JITTER

Peak-to-peak jitter, 10,000 cycles

33.3 MHz Output

66.6 MHz Output

44.9

133.3 MHz Output

65.4

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