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AD9576BCPZ Datasheet(PDF) 2 Page - Analog Devices |
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AD9576BCPZ Datasheet(HTML) 2 Page - Analog Devices |
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2 / 65 page ![]() AD9576 Data Sheet Rev. A | Page 2 of 65 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Conditions ..................................................................................... 4 Supply Current Specifications..................................................... 4 Power Dissipation Specifications ............................................... 5 Reference Inputs ........................................................................... 6 Reference Switchover Output Disturbance Specifications...... 6 PLL0 Characteristics .................................................................... 7 PLL1 Characteristics .................................................................... 7 Clock Distribution Outputs Specifications............................... 7 Output Alignment and Startup Specifications ....................... 10 PLL0 Channels Absolute Clock Jitter Specifications ............. 11 PLL1 and Bypass Channel Absolute Clock Jitter Specifications .............................................................................. 13 OUT8 to OUT10 Channel Cycle to Cycle Clock Jitter Specifications .............................................................................. 13 Logic Input Pins Characteristics—REF_SEL, RESET, SPx, PPRx ............................................................................................. 14 Status Output Pins Characteristics—LD_0, LD_1, REF_SW, REF_STATUS, REF_ACT ......................................................... 14 Serial Control Port Specifications ............................................ 15 Absolute Maximum Ratings.......................................................... 17 Thermal Resistance .................................................................... 17 ESD Caution................................................................................ 17 Pin Configuration and Function Descriptions........................... 18 Typical Performance Characteristics ........................................... 22 Phase Noise and Voltage Waveforms....................................... 22 Reference Switching Frequency and Phase Disturbance ...... 24 Terminology .................................................................................... 25 Theory of Operation ...................................................................... 26 Overview...................................................................................... 26 Reference Inputs ......................................................................... 26 Reference Monitor...................................................................... 27 Reference Switching ................................................................... 28 PLL0 Integer-N/Fractional-N PLL........................................... 29 PLL1 Integer-N PLL................................................................... 35 Output Distribution ................................................................... 36 PPRx Pins .................................................................................... 38 Power-On Reset (POR) ............................................................. 41 Serial Control Port ......................................................................... 42 SPI/I²C Port Selection................................................................ 42 SPI Serial Port Operation.......................................................... 42 I2C Serial Port Operation .......................................................... 44 Control Register Map..................................................................... 48 Control Register Descriptions ...................................................... 51 Serial Port Configuration Registers (Register 0x000 to Register 0x00F) ........................................................................... 51 Status Indicator Registers (Register 0x020 to Register 0x021) .. 52 Chip Mode Register (Register 0x040) ..................................... 52 Reference Input Configuration Registers (Register 0x080 to Register 0x081) ........................................................................... 53 Reference Switchover Registers (Register 0x082 to Register 0x083) ........................................................................... 54 PLL0 Configuration Registers (Register 0x100 to Register 0x111) ........................................................................... 55 PLL0 VCO Dividers Registers (Register 0x120 to Register 0x122) ........................................................................... 57 PLL0 Distribution Registers (Register 0x140 to Register 0x14D) .......................................................................... 58 PLL1 Configuration Registers (Register 0x200 to Register 0x202) ........................................................................... 60 PLL1 Distribution Registers (Register 0x240 to Register 0x246) ........................................................................... 60 Applications Information .............................................................. 63 Interfacing to CMOS Clock Outputs....................................... 63 Interfacing to LVDS and HSTL Clock Outputs ..................... 63 Interfacing to HCSL Clock Outputs ........................................ 63 Power Supply............................................................................... 64 Power and Grounding Considerations and Power Supply Rejection...................................................................................... 64 Outline Dimensions ....................................................................... 65 Ordering Guide .......................................................................... 65 |
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