AD5293 datasheet(7/24 Pages) AD

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Data Sheet

AD5293

Rev. E | Page 7 of 24

INTERFACE TIMING SPECIFICATIONS

VDD = VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, and −40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted.

Table 5.

Parameter

Limit1

Unit

Test Conditions/Comments

t12

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC to SCLK falling edge setup time

ns min

Data setup time

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

4003

ns min

Minimum SYNC high time

ns min

SYNC rising edge to next SCLK fall ignored

t104

ns min

RDY rise to SYNC falling edge

t114

ns max

SYNC rise to RDY fall time

t124

2.4

µs max

RDY low time, RDAC register write command execute time (resistor performance mode)

t124

410

ns max

RDY low time, RDAC register write command execute time (normal mode)

t124

1.5

ms max

Software\hardware reset

t134

450

ns max

RDY low time, RDAC register read command execute time

t144

450

ns max

SCLK rising edge to SDO valid

tRESET

ns min

Minimum RESET pulse width (asynchronous)

tPOWER-UP5

ms max

Power-on time to half scale

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Maximum SCLK frequency = 50 MHz.

Refer to t12 and t13 for RDAC register commands operations.

RPULL_UP = 2.2 kΩ to VLOGIC with a capacitance load of 168 pF.

Typical power supply voltage slew-rate of 2 V/ms.

DATA BITS

DB9 (MSB)

DB0 (LSB)

CONTROL BITS

Figure 2. Shift Register Contents

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