AD5293

Data Sheet

Rev. E | Page 10 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESET

A

W

RDY

SYNC

SCLK

B

EXT_CAP

1

2

3

4

5

6

7

DIN

GND

14

13

12

11

10

9

8

AD5293

TOP VIEW

Not to Scale

SDO

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

RESET

Hardware Reset Pin. Sets the RDAC register to midscale. RESET is activated at the logic high transition. Tie RESET to

2

Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 µF ceramic

capacitors and 10 µF capacitors.

3

A

4

W

5

B

6

Positive Power Supply. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.

7

EXT_CAP

Connect a 1 µF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V.

8

Logic Power Supply, 2.7 V to 5.5 V. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.

9

GND

Ground Pin, Logic Ground Reference.

10

DIN

Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input.

11

SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be

transferred at rates up to 50 MHz.

12

SYNC

Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes

low, it enables the shift register, and data is transferred in on the falling edges of the following clocks. The selected

13

SDO

Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data

from the serial register in daisy-chain mode or in readback mode.

14

RDY

Ready Pin. This active-high, open-drain output identifies the completion of a write or read operation to or from

the RDAC register.