XC161CS-32F datasheet(48/84 Pages) INFINEON

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XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.14

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can be disabled

until the EINIT instruction has been executed (compatible mode), or it can be disabled

and enabled at any time by executing instructions DISWDT and ENWDT (enhanced

mode). Thus, the chip’s start-up procedure is always monitored. The software has to be

designed to restart the Watchdog Timer before it overflows. If, due to hardware or

software related failures, the software fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls the RSTOUT pin low in order to allow

external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by

2/4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified

reload value (stored in WDTREL) in order to allow further variation of the monitored time

interval. Each time it is serviced by the application software, the high byte of the

Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between

µs and 419 ms can be monitored (@ 40 MHz).

The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).

XC161CS-32F Datasheet(PDF) 48 Page - Infineon Technologies AG