XC161CS-32F datasheet(74/84 Pages) INFINEON

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XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

Variable Memory Cycles

External bus cycles of the XC161 are executed in five subsequent cycle phases (AB, C,

D, E, F). The duration of each cycle phase is programmable (via the TCONCSx

registers) to adapt the external bus cycles to the respective external module (memory,

peripheral, etc.).

The duration of the access phase can optionally be controlled by the external module via

the READY handshake input.

This table provides a summary of the phases and the respective choices for their

duration.

Note: The bandwidth of a parameter (minimum and maximum value) covers the whole

operating range (temperature, voltage) as well as process variations. Within a

given device, however, this bandwidth is smaller than the specified range. This is

also due to interdependencies between certain parameters. Some of these

interdependencies are described in additional notes (see standard timing).

Table 19

Programmable Bus Cycle Phases (see timing diagrams)

Bus Cycle Phase

Parameter Valid Values Unit

Address setup phase, the standard duration of this

phase (1 … 2 TCP) can be extended by 0 … 3 TCP

if the address window is changed

1 … 2 (5)

TCP

Command delay phase

0 … 3

TCP

Write Data setup/MUX Tristate phase

0 … 1

TCP

Access phase

1 … 32

TCP

Address/Write Data hold phase

0 … 3

TCP

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