XC161CS-32F datasheet(75/84 Pages) INFINEON

75 / 84 page

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

Note: The shaded parameters have been verified by characterization.

They are not subject to production test.

Table 20

External Bus Cycle Timing (Operating Conditions apply)

Parameter

Symbol

Limits

Unit

Min.

Max.

Output valid delay for:

RD, WR(L/H)

115

Output valid delay for:

BHE, ALE

-1

Output valid delay for:

A23 … A16, A15 … A0 (on PORT1)

318

Output valid delay for:

A15 … A0 (on PORT0)

318

Output valid delay for:

316

Output valid delay for:

D15 … D0 (write data, MUX-mode)

319

Output valid delay for:

D15 … D0 (write data, DEMUX-mode)

216

Output hold time for:

RD, WR(L/H)

-3

4ns

Output hold time for:

BHE, ALE

Output hold time for:

A23 … A16, A15 … A0 (on PORT0)

Output hold time for:

-2

4ns

Output hold time for:

D15 … D0 (write data)

Input setup time for:

READY, D15 … D0 (read data)

–

Input hold time

READY, D15 … D0 (read data)1)

-5

–

1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge

of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read

data can be removed after the rising edge of RD.

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