AD9171 datasheet(21/133 Pages) AD

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Data Sheet

AD9171

Rev. 0 | Page 21 of 133

Multibyte data transfers can be performed as well by holding

the CS pin low for multiple data transfer cycles (eight SCLKs)

after the first data transfer word following the instruction cycle.

The first eight SCLKs following the instruction cycle read from

or write to the register provided in the instruction cycle. For

each additional eight SCLK cycles, the address is either incre-

mented or decremented and the read/write occurs on the new

ADDRINC_M (Register 0x000, Bit 5 and Bit 2). When ADDRINC

or ADDRINC_M is 1, the multicycle addresses are incremented.

When ADDRINC or ADDRINC_M is 0, the addresses are decre-

mented. A new write cycle can always be initiated by bringing

CS high and then low again.

To prevent confusion and to ensure consistency between devices,

the chip tests the first nibble following the address phase, ignoring

the second nibble. This test is completed independently from the

LSB first bits and ensures that there are extra clock cycles following

the soft reset bits (Register 0x000, Bit 0 and Bit 7). This test of

the first nibble only applies when writing to Register 0x000.

R/W A14 A13

A0 D7

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

Figure 22. Serial Register Interface Timing, MSB First,

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

Figure 23. Serial Register Interface Timing, LSB First,

SCLK

SDIO

DATA BIT n – 1

DATA BIT n

tDV

Figure 24. Timing Diagram for Serial Port Register Read

SCLK

SDIO

INSTRUCTION BIT 14

INSTRUCTION BIT 0

INSTRUCTION BIT 15

tDS

tDH

tPWH

tPWL

Figure 25. Timing Diagram for Serial Port Register Write

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