AD9171 datasheet(29/133 Pages) AD

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Data Sheet

AD9171

Rev. 0 | Page 29 of 133

40B

SYNCING LMFC SIGNALS

The AD9171 requires a synchronization (sync) to align the

LMFC and other internal clocks before the SERDES links are

brought online. The synchronization is a one-shot sync, where

the synchronization process begins on the next edge of the

alignment signal following the assertion of the SYSREF_MODE_

ONESHOT control in Register 0x03A, Bit 1.

In Subclass 1, the SYSREF± rising edge acts as the alignment edge;

in Subclass 0, an internal processing clock acts as the alignment

edge. When a sync has completed, the SYNC_ROTATION_

DONE (Register 0x03A, Bit 4) bit is asserted and remains

asserted until another sync is requested.

After a synchronization occurs, the JESD204B link can be

enabled. In Subclass 1, the latency of the JESD204B system is

deterministic and allows synchronization across multiple

devices, if desired.

68B

SYSREF± Signal

The SYSREF± signal is a differential source synchronous input

that synchronizes the LMFC signals in both the transmitter and

receiver in a JESD204B Subclass 1 system to achieve deterministic

latency.

The SYSREF± signal is a rising edge sensitive signal that is

sampled by the device clock rising edge. It is best practice that

the device clock and SYSREF± signals be generated by the same

source, such as the HMC7044 clock generator, so that the phase

alignment between the signals is fixed. When designing for

optimum deterministic latency operation, consider the timing

distribution skew of the SYSREF± signal in a multipoint link

system (multichip).

The AD9171 supports a periodic SYSREF± signal. The periodicity

can be continuous, strobed, or gapped periodic. The SYSREF±

signal can be dc-coupled with a common-mode voltage of 0.6 V

to 2.2 V and differential swing of 200 mV p-p to 1 V p-p. When dc-

coupled, a small amount of common-mode current (up to 0.3 mA)

is drawn from the SYSREF± pins. See Figure 58 and Figure 59 for

the SYSREF± internal circuit for dc-coupled and ac-coupled

configurations. Ensure that the SYSREF_INPUTMODE bit

(Register 0x084, Bit 6) is set to 1, dc-coupled, to prevent

overstress on the SYSREF± receiver pins.

10.3kΩ

240F

DC SYSREF± MODE

104Ω

SYSREF–

SYSREF+

104Ω

100Ω

240F

10.3kΩ

130kΩ

VCM

Figure 35. DC-Coupled SYSREF± Receiver Circuitry

10.3kΩ

240F

AC SYSREF± MODE

104Ω

SYSREF–

SYSREF+

104Ω

100Ω

240F

10.3kΩ

130kΩ

VCM

Figure 36. AC-Coupled SYSREF± Receiver Circuitry

To avoid this common-mode current draw, the SYSREF± receiver

can be ac-coupled using a 50% duty cycle periodic SYSREF±

signal with ac coupling capacitors. If ac-coupled, the ac coupling

capacitors combine with the resistors shown in Figure 59 to

make a high-pass filter with an RC time constant of τ = RC.

Select C such that τ > 4/SYSREF± frequency. In addition, the

edge rate must be sufficiently fast to allow SYSREF± sampling

clocks to correctly sample the rising SYSREF± edge before the

next sample clock.

When ac coupling the SYSREF± inputs, ensure that the

SYSREF_INPUTMODE bit (Register 0x084, Bit 6) is set to 0,

ac-coupled, to enable the internal receiver biasing circuitry and

prevent overstress on the SYSREF± receiver pins. AC coupling

allows a differential voltage swing from 200 mV to 1 V on the

SYSREF± pins.

69B

SYSREF± Sampling

The SYSREF± signal is sampled by a divide by 4 version of the

DAC clock. Thus, the minimum pulse width of the SYSREF±

signal must exceed four DAC clock periods to ensure accurate

sampling. The timing between the SYSREF± and DAC clock

input signal does not need to be timing constrained and the

amount of deterministic latency variation in Subclass 1 is within

±2.5 DAC clock cycles at 6 GHz.

By default, the first SYSREF± rising edge at the SYSREF± inputs

detected after asserting the SYSREF_MODE_ONESHOT bit

(Register 0x03A, Bit 1) begins the sync and aligns the internal

LMFC signal with the sampled SYSREF± edge.

SYSREF± edges are ignored after the SYSREF_MODE_ONESHOT

bit is asserted before the synchronization takes place. For example,

if SYSREF_COUNT is set to 3, the AD9171 does not sync after

the SYSREF_MODE_ONESHOT bit is asserted until the arrival

of the fourth SYSREF± edge.

70B

SYSREF± Jitter IRQ

In Subclass 1, after the one-shot synchronization occurs, the

SYSREF± signal is monitored to ensure that the subsequent

SYSREF± edges do not deviate from the internal LMFC clock

by more than a target amount.

the error window allowed, in DAC clock units. If a SYSREF±

edge varies from the internal LMFC clock by more than the

number of DAC clock units set in SYSREF_ERR_WINDOW,

the IRQ_SYSREF_JITTER is asserted.

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