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LTC2000A Datasheet(PDF) 1 Page - Analog Devices |
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LTC2000A Datasheet(HTML) 1 Page - Analog Devices |
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1 / 54 page  LTC2000A 1 2000afb For more information www.linear.com/LTC2000A BLOCK DIAGRAM FEATURES DESCRIPTION 16-/14-/11-Bit 2.7Gsps DACs The LTC®2000A is a family of 16-/14-/11-bit 2.7Gsps current steering DACs with exceptional spectral purity. The single (1.35Gsps mode) or dual (2.7Gsps mode) port source synchronous LVDS interface supports data rates of up to 1.35Gbps using a 675MHz DDR data clock, which can be either in quadrature or in phase with the data. An internal synchronizer automatically aligns the data with the DAC sample clock. Additional features such as pattern generation, LVDS loopout and junction temperature sensing simplify system development and testing. A serial peripheral interface (SPI) port allows configura- tion and read back of internal registers. Operating from 1.86V and 3.3V supplies, the LTC2000A consumes 2.41W at 2.7Gsps and 1.43W at 1.35Gsps. APPLICATIONS n 80dBc SFDR at 50MHz fOUT n >68dBc SFDR from DC to 1080MHz fOUT n 40mA Nominal Full-Scale, ±1V Output Compliant n 10mA to 60mA Adjustable Full-Scale Current Range n Single or Dual Port DDR LVDS and DHSTL Interface n Low Latency (7.5 Cycles for Single Port, 11 Cycles for Dual Port) n >78dBc 2-Tone IMD from DC to 1000MHz fOUT n –156dBc/Hz Additive Phase Noise at 1MHz Offset for 65MHz fOUT n 170-Lead (9mm × 15mm) BGA Package n Broadband Communication Systems n DOCSIS CMTS n Direct RF Synthesis n Radar n Instrumentation n Automatic Test Equipment All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 8330633. 4:1 TSTP/N PD CS SCK SDI SDO SVDD 50Ω IOUTP IOUTN FSADJ REFIO 50Ω 10k 2000A BD CKP/N GND DVDD33 DVDD18 AVDD33 AVDD18 GAIN ADJUST CLOCK SYNC CLK RECEIVER DELAY ADJUST DCKOP/N DCKIP/N DBP/N[15:0] DAP/N[15:0] CLK DIVIDER ÷2 OR ÷4 REF SPI PATTERN GENERATOR JUNCTION TEMPERATURE 16-BIT DAC fOUT (MHz) 0 50 60 70 80 90 100 200 400 600 800 2000A TA01b 1000 1200 DIGITAL AMPLITUDE = 0dBFS IOUTFS = 40mA SFDR vs fOUT, fDAC = 2.7Gsps |
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