LTC2000A datasheet(19/54 Pages) AD

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LTC2000A

2000afb

For more information www.linear.com/LTC2000A

OPERATION

TIMING DIAGRAMS

SDI

SDO

SCK

t13

t10

Hi-Z

2000A F01

DAP/N, DBP/N

t12

DCKI

t11

2000A F02

t12

t11

DAP/N, DBP/N

t11

DCKI

t12

2000A F03

t11

t12

Figure 1. Serial Interface Timing

Figure 2. LVDS Interface Timing (DCKI_Q = 0, DCK_TADJ = 000)

Figure 3. LVDS Interface Timing (DCKI_Q = 1)

Introduction

The LTC2000A is a family of 2.7Gsps current steering

DACs. Three resolutions (16-, 14-, 11-bit) are available

in a 170-lead BGA package. The LTC2000A features high

output bandwidth and output current, while maintaining

a clean output spectrum with low spurs, making it ideal

for generating high frequency or broadband signals. The

LTC2000A output current is nominally 40mA and is a

scaled (16x) replica of the current flowing out of the FSADJ

pin (nominally 2.5mA). The high output current allows

flexibility in the output impedance, and the high FSADJ

current and low scaling factor give excellent close-in phase

noise performance.

The LTC2000A has two 16-, 14-, 11-bit wide LVDS or

DHSTL-compatible parallel data input ports (DAP/N,

DBP/N). Each data input port is capable of receiving two’s

complement data at up to 1.35Gbps using a double data

rate (DDR) data input clock (DCKIP/N) at up to 675MHz.

The DDR data input clock may be either in quadrature or

in phase with the data arriving on the data input ports.

LTC2000A Datasheet(PDF) 19 Page - Analog Devices

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